| Age | Commit message (Collapse) | Author |
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SConscript:
comment out most devices
add vport.cc
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
push in alpha name space
fix for new memory system
arch/alpha/faults.cc:
arch/alpha/faults.hh:
Added an unimplemented fault that can be returned if a certain
function isn't implemented
arch/alpha/freebsd/system.cc:
arch/alpha/linux/system.cc:
arch/alpha/stacktrace.cc:
arch/alpha/system.cc:
arch/alpha/tlb.hh:
arch/alpha/tru64/system.cc:
fixed for new memory system
arch/alpha/tlb.cc:
fixed for new memory system
removed code that seems to have no purpose
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
fixed for new memory system
put in namespace AlphaISA
base/remote_gdb.cc:
fix for new memory system
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/exec_context.hh:
create two ports one of physical accesses and one for superpage accesses
Add functions getVirtPort() getPhysPort() delVirtPort(). To get statically
allocated physical or virtual ports or if an execcontext is passed in
get a dynamically allocated virtual port
dev/alpha_console.cc:
dev/alpha_console.hh:
Redo for new memory system
dev/io_device.cc:
dev/io_device.hh:
new I/O devices for new memory system
kern/linux/events.cc:
kern/linux/printk.cc:
kern/linux/printk.hh:
kern/tru64/dump_mbuf.hh:
kern/tru64/printf.cc:
kern/tru64/printf.hh:
Arguments now in namespaces
kern/tru64/tru64_events.cc:
mem/bus.cc:
fix for new memory syste
mem/physical.hh:
new addressranges function
getPort should be public
mem/port.hh:
Add write/read methods to functional port
update getDeviceAddrRanges to have a list of both snoops and response lists
sim/pseudo_inst.cc:
sim/system.cc:
sim/system.hh:
Update for new mem system
sim/vptr.hh:
comment out code and replace with panics
This will need to be fixed at some point, but it's not easy.
--HG--
extra : convert_revision : 41f41f422cfbab3751284d55cccb6ea64a7956e2
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SE mode now has a port that goes to whatever toplevel mem object the
CPU sees that does the appropriate translation for syscall emulation
SConscript:
translating port is a syscall emu only source
arch/alpha/system.cc:
base/loader/object_file.cc:
base/loader/object_file.hh:
Use the new functional port to write the binaries into memory
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/simple/cpu.cc:
We aren't always going to be writing straight to memory with syscalls
support writing to a cache
mem/port.hh:
Add a simple unidirectional functional port that panics on any incoming requests
mem/translating_port.hh:
make translating port inherit from the simple port
sim/system.cc:
sim/system.hh:
Add a functional port that is used to load the original binaries
--HG--
extra : convert_revision : 9096866d0b23e3aceea68394abb76e63c0f8fd8d
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arch/alpha/arguments.cc:
rather than returning 0, put a panic in... it will actually make us fix
this rather than scratching our respective heads
base/loader/object_file.cc:
base/loader/object_file.hh:
Object loader now takes a port rather than a translating port
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
sim/process.cc:
Make translating port a type of port rather than anything special
cpu/simple/cpu.cc:
no need to grab a port from the cpu anymore
mem/physical.cc:
add an additional type of port to physicalmemory called "functional"
Only used for functional accesses (loading binaries/syscall emu)
mem/port.hh:
make readBlok/writeBlob virtual so translating port can do the
translation first
mem/translating_port.cc:
mem/translating_port.hh:
Make TranslatingPort inherit from Port
sim/system.cc:
header file that doesn't exit removed
--HG--
extra : convert_revision : 89b08f6146bba61f5605678d736055feab2fe6f7
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arch/alpha/arguments.cc:
There will not be a phys mem ptr in the XC in the newmem. This read will have to go through something else.
arch/alpha/ev5.cc:
Remove instantiations of these functions for the FastCPU, as the FastCPU is not really used. Also this messed up the ability to specify which CPU models are being built.
cpu/exec_context.hh:
Remove getPhysMemPtr() function.
cpu/exetrace.cc:
Include sim/system.hh, and sort the includes.
cpu/simple/cpu.cc:
Fixes for full system compilation.
kern/system_events.cc:
Remove include of encumbered FullCPU. The branch prediction will need to be fixed up in a more generic way in the future.
--HG--
extra : convert_revision : a8bbf562a277aa80e8f40112570c0a825298a05c
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fix tlbs for newmem
SConscript:
page_table.cc is a syscall only kinda thing
arch/alpha/tlb.cc:
arch/alpha/tlb.hh:
fix tlbs for newmem
--HG--
extra : convert_revision : 0aafcb9698b993a807be883bde1696ee4d33b408
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--HG--
extra : convert_revision : 111af292373edebcd106938e76610f9ac4a6ce58
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into zeep.eecs.umich.edu:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision : 5ab4ce9f6ec7af326d8906060ae3558cfd67ca08
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don't ever include a file while in a namespace
start of making alpha console new memsystem happy
Make a BasePioDevice which is what all the simple Pio devices will inherit from
add a description of when the data pointer will have memory
arch/alpha/isa_traits.hh:
don't ever include a file while in a namespace
dev/alpha_console.cc:
dev/alpha_console.hh:
start of making alpha console new memsystem happy
dev/io_device.cc:
dev/io_device.hh:
Make a BasePioDevice which is what all the simple Pio devices will inherit from
mem/packet.hh:
add a description of when the data pointer will have memory
--HG--
extra : convert_revision : 495c0915541f9cad3eb42891e60b4ecbee7952bf
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--HG--
extra : convert_revision : c580bc6bd308fd502fb5a14ea84b5214e1d2718e
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This causes a crash if you're using scons 0.96.1 *and* you specify
more than one CPU model. Since the .isa scanner now works with 0.96.91
then upgrading should not be an issue. For now we're only using one CPU
model (SimpleCPU) so there isn't even a pressing need to upgrade yet.
build/SConstruct:
Make CPU_MODELS a sticky option.
This causes a crash if you're using scons 0.96.1 *and* you specify
more than one CPU model. Since the .isa scanner now works with 0.96.91
then upgrading should not be an issue. For now we're only using one CPU
model (SimpleCPU) so there isn't even a pressing need to upgrade yet.
--HG--
extra : convert_revision : d8319c4cd5c937c2c033270cef850d19b805d256
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--HG--
extra : convert_revision : 15bcdb3a6552ad8ee070677c9464ae1302768068
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The latter causes multiple variable definitions if the same operand
is used as both a src and a dest.
arch/alpha/isa/mem.isa:
arch/mips/isa/formats/mem.isa:
Use op_decl instead of op_src_decl + op_dest_decl.
The latter causes multiple variable definitions if the same operand
is used as both a src and a dest.
--HG--
extra : convert_revision : c14d91b293d3afef45c8728d3d8784f372c0b7f4
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(which wasn't working since panic() isn't declared yet here).
arch/alpha/faults.hh:
Make ItbFault methods abstract instead of calling panic()
(which wasn't working since panic() isn't declared yet here).
--HG--
extra : convert_revision : b15242baa370777f265a3f6b7d5f5c05702b016f
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Makes .isa files cleaner and simplifies scanner too.
Simplified scanner to work under both old and new versions of scons.
arch/SConscript:
Simplify .isa scanner... seems to work with both scons 0.96.1 and 0.96.91 now.
Assumes .isa ##include paths are relative to including file.
arch/alpha/isa/main.isa:
arch/mips/isa/formats/formats.isa:
arch/mips/isa/main.isa:
arch/sparc/isa/formats.isa:
arch/sparc/isa/main.isa:
Make ##include paths relative to including file.
arch/isa_parser.py:
Make ##include file paths relative to including file.
Makes .isa files cleaner and simplifies scanner too.
Partial rewrite of include-handling code to use cool re.sub() feature
where you can specify a function to provide the replacement string.
Minor cleanup of error-handling code.
Also got rid of '#!' at top to make caller choose which python interpreter
is used (since SPARC now requires 2.4 to build, we may need to do that via
scons in the future).
--HG--
rename : arch/mips/isa/formats.isa => arch/mips/isa/formats/formats.isa
extra : convert_revision : 15a3920fa3aaf80cd94083eda853aa4e49425045
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into ewok.(none):/home/gblack/m5/newmem
--HG--
extra : convert_revision : 7effd744f9061d4aa8e9c3fa769115dfa73cbb79
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arch/sparc/isa/decoder.isa:
Replaced register number munging with RdLow and RdHigh operands.
arch/sparc/isa/formats/mem.isa:
Fixed how the address calculation code is dealt with.
arch/sparc/isa/operands.isa:
Changed the tabbing so that the whole oeprands block was consistent, and added RdLow and RdHigh operands. These registers are used when Rd is meant to refer to a pair of registers, rather than just one.
arch/sparc/isa_traits.hh:
Moved some functions to the new (to SPARC) utility.hh file. Also, dummy Fpcr_DepTag and Uniq_DepTag DepTags were added to pacify Tru64. These need to be removed, and Tru64 needs to not be compiled in if it isn't appropriate.
arch/sparc/regfile.hh:
Changed regSpace to have the correct size.
arch/sparc/utility.hh:
A new file for sparc to match the one for alpha.
--HG--
extra : convert_revision : ff6b529093d15f327ec11f067ad533bacdba9932
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through its own fault() method; this is handled by the fault's invoke() methods.
arch/alpha/faults.cc:
Move TLB fault code into the normal fault invoke() method.
arch/alpha/faults.hh:
Move DTB/ITB fault handling code into their own class with a specific invoke() method. Have DTB/ITB faults derive from these classes.
Unfortunately the DtbAlignmentFault is somewhat odd; it's a normal alignment fault, but it must also set some specific IPRs.
arch/alpha/tlb.cc:
arch/alpha/tlb.hh:
Setting IPRs is now handled through the fault itself.
--HG--
extra : convert_revision : 5cb92ce2186ff79f632bfcbc9ba62a8a04400eae
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into ewok.(none):/home/gblack/m5/newmem
--HG--
extra : convert_revision : 762df7bf15e8e22a8fab8bbcd933047d1c8cdfa9
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arch/sparc/isa/decoder.isa:
Fixed comments so they don't comment out the ending braces of the format specifier.
--HG--
extra : convert_revision : 3f037c0a17abd0dff71d22fdcd95959c3670e88a
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change getPort parameter from char* to string
Add an extra phase between construction and init called connect
SConscript:
Add the bus and connector objects to scons
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
the connection to memory shouldn't be made until we know the memory
object exists (e.g. after construction)
dev/io_device.hh:
change to const string
mem/bus.hh:
change getPort parameter from char* to string
initialize num_interfaces
mem/mem_object.hh:
change getPort parameter from char* to string
mem/physical.cc:
mem/physical.hh:
change getPort parameter from char* to string
get rid of the bus object I created last time
python/m5/objects/PhysicalMemory.py:
get rid of the bus object I created last time
sim/main.cc:
sim/sim_object.cc:
sim/sim_object.hh:
Add an extra phase between construction and init called connect
--HG--
extra : convert_revision : 0e994f93374fa72a06d291655c440ff1b8e155a9
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--HG--
extra : convert_revision : 96b5494b7d0b5ca702ac69cfa0bf8c4d44e1cc3b
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requestTime -> time
responseTime -> packet.time
Make CPU and memory able to connect to the bus
dev/io_device.cc:
update for request and packet both having a time
hand platform off to port for eventual selection of request modes
dev/io_device.hh:
update for request and packet both havig a time
hand platform off to port for eventual selection of request modes
mem/bus.hh:
Add a device map struct that maps a range to a portId
- Which needs work it theory it should be an interval tree
- but it is a list and works fine right now
Add a function called findPort which returns port for an addr range
Add a deviceBlockSize function that really shouldn't exist, but it
was easier than fixing the translating port
mem/packet.hh:
add a time to each packet
mem/physical.cc:
mem/physical.hh:
python/m5/objects/PhysicalMemory.py:
Make physical memory take a MemObject parameter of what to connect to
mem/request.hh:
remove requestTime/responseTime for just time in request which
is requset time and the time in the packet which is responsetime
python/m5/objects/BaseCPU.py:
Instead of memory cpu connects to any memory object
python/m5/objects/Bus.py:
Fix for new bus object
--HG--
extra : convert_revision : 72605e8a3fcdd9e80a41f439909ee7feb3f1fe1d
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into zeep.eecs.umich.edu:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision : 45dba22ecbdfc8e1bb0df1efd06a37f40d56b67f
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Add another type to the PacketResult enum of Unknown
Seperate time into requsetTime and responseTime.
dev/io_device.cc:
dev/io_device.hh:
Make PioPort/DmaPort,DmaDevice/PioDevice compile.
mem/packet.hh:
Add another type to the PacketResult enum of Unknown (e.g. no state set yet)
mem/request.hh:
Seperate time into requsetTime and responseTime.
--HG--
extra : convert_revision : c6394cb838013296caea6492275252b8cae2882f
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into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-mips
--HG--
extra : convert_revision : db8490e41ec17fc8f4e2dc9548ecdc7d28b4cdd1
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arch/mips/isa/base.isa:
disassembly fixes
arch/mips/isa/decoder.isa:
support for unaligned loads/stores
arch/mips/isa_traits.hh:
edit Syscall Reg values
arch/mips/linux_process.cc:
call writevFunc on writev syscall
--HG--
extra : convert_revision : 4aea6d069bd7ba0e83b23d2d85c50d68532f0454
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into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
sim/process.cc:
Fix bad auto merge (m5 changes unnecessary in newmem).
--HG--
extra : convert_revision : a3ced4cd1668cd47bd02430872ca68b1433aae98
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arch/mips/isa_traits.hh:
use syscall return function from alpha
arch/mips/linux_process.cc:
fix some syntax errors, map some functions to the desc. table
--HG--
extra : convert_revision : 75e8e8893b7d96bb4fc8e8eced53bd16c0a727d1
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into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-mips
--HG--
extra : convert_revision : 1646b4fb065e3ed9d8de22e3f5c3aa05a2ef01b6
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arch/mips/isa/decoder.isa:
arch/mips/isa_traits.hh:
sim/syscall_emul.cc:
make syscall instruction functional
arch/mips/linux_process.cc:
add all MIPS/Linux syscalls to descriptor list
--HG--
extra : convert_revision : 5455a345e76be921e9f63b248aef874b6358e465
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--HG--
extra : convert_revision : 2ffbfc4755e46a119c9709d6a5e9ddc41fde45e0
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into ewok.(none):/home/gblack/m5/newmem
arch/sparc/isa/decoder.isa:
Hand merged
--HG--
extra : convert_revision : 5d5338602c48be48978972a091c5e93f9dd775aa
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--HG--
extra : convert_revision : 4a73507206cf287a89e1d496b2a08cfd1fafdf4d
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--HG--
extra : convert_revision : c4e66cd678313f7fe169787cb1bf3e45f114c4fd
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put back in Tcc code that was deleted in last merge
arch/sparc/isa/bitfields.isa:
clean up condition codes a little bit
--HG--
extra : convert_revision : c554fd5c3ee8cfd6643f69f8351124a7a4b5d9fa
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--HG--
extra : convert_revision : fe4b7dc5b7d583e1d890648ba98bb0daf722a704
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into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-mips
--HG--
extra : convert_revision : 02fe0b0170348dc6f6a985c15123806088a8c23e
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while
before getting in a infinite loop. It actually "tries" to syscall too, but syscalls
aren't implemented just yet
arch/mips/faults.cc:
more descriptive names for faults (will help future users as well as me!)
arch/mips/isa/base.isa:
make sure we are printing out "BasicOp" format disassembly instructions as dest,src,src instead of src,src,dest
arch/mips/isa/decoder.isa:
FIX LW/SW Bug!!!! I was actually loading a byte instead of a word
FIX JALR Bug!!!! I was not saving the link address in R31 for this instruction
FIX SLL/NOP Bug!!! We now recognize the varying flavors of sll,nop,ehb,& ssnop correctly
base/loader/elf_object.cc:
change back to original way
base/loader/elf_object.hh:
change back to original!
--HG--
extra : convert_revision : 39b65fba31c1842ac6966346fe8a35816a4231fa
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into ewok.(none):/home/gblack/m5/newmem
arch/sparc/isa/decoder.isa:
SCCS merged
--HG--
extra : convert_revision : 460843b49bc96b3fbc5897828c23f9cf9b010ae0
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arch/alpha/types.hh:
Moved the DependenceTags enum from types to constants.
arch/sparc/faults.cc:
arch/sparc/faults.hh:
Corrected a misspelling of PriviledgeOpcode and PrivilegedAction.
arch/sparc/isa/formats.isa:
Fixups towards compiling. Added a few additional instruction formats.
--HG--
extra : convert_revision : 4c5506877b71b8a5c8c45db41192cf759cdac374
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building.
--HG--
extra : convert_revision : 2c2562da323fa1249af72af3a89c7666c745ae2b
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base/loader/elf_object.cc:
Print warning if there are more than two loadable segments.
We currently assume there are at most two (text & data), and that's
held so far, but it would be nice not to silently ignore others.
--HG--
extra : convert_revision : 1b3e693e95ba1210b09528b97819a7fa86426edc
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into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-mips
--HG--
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arch/sparc/isa/bitfields.isa:
the trap field is 7:0
arch/sparc/isa/decoder.isa:
add code to in the Tcc instruction to call a syscall
arch/sparc/isa_traits.hh:
We need the syscall num register
--HG--
extra : convert_revision : 0861ec1dd8c7cac57765b22bc408fdffbe63fe2a
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/m5
--HG--
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--HG--
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is changed
Add a default machine width parameter
Arch based live processes
arch/alpha/linux/process.cc:
arch/alpha/linux/process.hh:
arch/alpha/process.cc:
arch/alpha/process.hh:
arch/alpha/tru64/process.cc:
arch/alpha/tru64/process.hh:
arch/mips/linux_process.cc:
arch/mips/process.cc:
arch/mips/process.hh:
arch/sparc/linux/process.cc:
arch/sparc/linux/process.hh:
arch/sparc/process.cc:
arch/sparc/process.hh:
configs/test/test.py:
python/m5/objects/Process.py:
sim/process.cc:
sim/process.hh:
Architecture based live processes
arch/mips/isa_traits.hh:
arch/sparc/isa_traits.hh:
Add a default machine width parameter
mem/port.hh:
gcc 4 really wants a virtual destructor
sim/byteswap.hh:
remove the comment around long and unsigned long even though uint32_t
and int32_t are defined. Seems to work with gcc 4 and 3.4.3.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
add translations for new sections that are mmapped or when the brk
is changed
--HG--
extra : convert_revision : e2f9f228113c7127c87ef2358209a399c30ed5c6
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configs/test/hello_mips:
hello world mips binary
--HG--
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arch/mips/isa/formats/branch.isa:
let user know that we alter r31 in disassembly
arch/mips/isa_traits.cc:
add copyRegs function ...
comment out serialize float code for now
arch/mips/isa_traits.hh:
make FloatRegFile a class ... change values of architectural regs
arch/mips/process.cc:
change MIPS to Mips
base/loader/elf_object.cc:
get global pointer initialized to a value
base/loader/elf_object.hh:
Add global_ptr to elf_object constructor
base/loader/object_file.hh:
MIPS to Mips
base/traceflags.py:
SimpleCPU trace flag
cpu/simple/cpu.cc:
DPRINTF flags for SimpleCPU
cpu/static_inst.hh:
Add Decoder functions to static_inst.hh
--HG--
extra : convert_revision : 0544a8524d3fe4229428cb06822f7da208c72459
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changed this in newmem.
--HG--
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