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2006-07-12Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem src/cpu/o3/fetch_impl.hh: Hand merge. --HG-- extra : convert_revision : 820dab2bc921cbadecaca51cd069327f984f5c74
2006-07-12Track the PC of the cache data stored in fetch so it doesn't access memory ↵Kevin Lim
multiple times if information is already in fetch. --HG-- extra : convert_revision : 00b160b255e998cf99286bcc21894110c7642624
2006-07-12Add --pdbNathan Binkert
src/python/m5/main.py: Add a command line option to invoke pdb on your script --HG-- extra : convert_revision : ef5a2860bd3f6e479fa80eccaae0cb5541a20b50
2006-07-12Merge m5.eecs.umich.edu:/bk/newmemNathan Binkert
into iceaxe.:/Volumes/work/research/m5/current --HG-- extra : convert_revision : 842a23da034c40c75364b76ca75de076da776ac6
2006-07-12Fix __file__ for scriptsNathan Binkert
src/python/m5/main.py: set __file__ to the script, not the m5 binary. --HG-- extra : convert_revision : a0bbd059d2fd321ae8ff68225abc8a7bb5c410ed
2006-07-11Add a cache version of FS (should really make this an option in original)Ron Dreslinski
Now to work on caches in FS, first steps: 1) LL/SC support (Top Level Cache Hooks) 2) Snooping in the bus (CSHR's for DMA Invalidates) --HG-- extra : convert_revision : b4e7984712f7dcd42649070c5ca538c87461e179
2006-07-11Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem --HG-- extra : convert_revision : 3be1aa4892aa8bbd458bdc5538bbcbd6c1ebe299
2006-07-11Fix ordering issue with squashed Icache Fetches and Static data in packet.Ron Dreslinski
Now hello world works with 2 levels of cache with O3 CPU(multiple outstanding requests). src/cpu/o3/fetch_impl.hh: Fix ordering issue with squashed Icache Fetches and Static data in packet. --HG-- extra : convert_revision : a6adb87540b007ead0b4982cb3f31da8199fb5ca
2006-07-11Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem --HG-- extra : convert_revision : c565fd7cebaa4058ba510b3db50a9c76bf301228
2006-07-11Fix option parsing.Nathan Binkert
src/python/m5/main.py: Don't allow interspersed arguments, it messes things up --HG-- extra : convert_revision : 8f1bcf4391f570741d92bf5420879862a48f6016
2006-07-10Migrate most of main() and and all option parsing to pythonNathan Binkert
configs/test/fs.py: configs/test/test.py: update for the new way that m5 deals with options src/python/SConscript: Compile AUTHORS, LICENSE, README, and RELEASE_NOTES into the python stuff. src/python/m5/__init__.py: redo the way options work. Move them all to main.py src/sim/main.cc: Migrate more functionality for main() into python. Namely option parsing src/python/m5/attrdict.py: A dictionary object that overrides attribute access to do item access. src/python/m5/main.py: The new location for M5's option parsing, and the main() routine to set up the simulation. --HG-- extra : convert_revision : c86b87a9f508bde1994088e23fd470c7753ee4c1
2006-07-10Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem --HG-- extra : convert_revision : c811eb9eacc480b14862f8074af80c56ec1e07f1
2006-07-10Some fixes so that MSHR's are matched and we don't issue overlapping ↵Ron Dreslinski
requests with detailed cpu src/mem/cache/base_cache.cc: If we still have outstanding requests, need to schedule event again src/mem/cache/miss/miss_queue.cc: Need to use block size so overlapping requests match in the MSHR's src/mem/cache/miss/mshr.cc: Actually save the address, otherwise we can't match MSHR's --HG-- extra : convert_revision : f0f018b89c2fb99f3ce8d6eafc0712ee8edeeda8
2006-07-10Minor fixes.Kevin Lim
src/cpu/checker/thread_context.hh: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: Change functions to match Korey's changes. src/cpu/ozone/lw_back_end.hh: Fix compile error. --HG-- extra : convert_revision : fb11ac2d6db3a75c1cdbad2c1c02f921ad7344a6
2006-07-10Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge --HG-- extra : convert_revision : 0e4c7684879b8552908e0b64a00b4824de807244
2006-07-10Some minor cleanups.Kevin Lim
src/cpu/SConscript: Change the error message to be slightly nicer. src/cpu/o3/commit.hh: Remove old code. src/cpu/o3/commit_impl.hh: Remove old unused code. --HG-- extra : convert_revision : 48aa430e1f3554007dd5e4f3d9e89b5e4f124390
2006-07-10Add parameters for backwards and forwards sizes for time buffers.Kevin Lim
src/base/timebuf.hh: Add a function to return the size of the time buffer. --HG-- extra : convert_revision : 8ffacd8b9013eb76264df065244e00dc1460efd4
2006-07-10Update config for a system with an L2Ron Dreslinski
--HG-- extra : convert_revision : c73a532ad6ad8d5115bda81fa778a4b97fbab713
2006-07-10Fix offset calculation. Now L2's work with timing&atomic.Ron Dreslinski
src/mem/packet.hh: Offset is based on packet, not request. --HG-- extra : convert_revision : d85af5838370541328ca35072c612d8198020625
2006-07-10Update FS configs to use cpu connectors for portsRon Dreslinski
--HG-- extra : convert_revision : 1e2e503401f92c1f30e2e487d7aeed1c7c5b7ee4
2006-07-10Fix cpu in full system to match SE.Ron Dreslinski
--HG-- extra : convert_revision : 95e422221ff5bab6104925d50a8882d31729b0f5
2006-07-07Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemKorey Sewell
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3 --HG-- extra : convert_revision : 9098d989832e2a5818b80771e3c02170c5c8cd5b
2006-07-07Support for recent port changes.Kevin Lim
src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/python/m5/objects/OzoneCPU.py: Support Ron's recent port changes. src/cpu/ozone/lw_back_end_impl.hh: Support Ron's recent port changes. Also support handling faults in SE. --HG-- extra : convert_revision : aa1ba5111b70199c052da3e13bae605525a69891
2006-07-07Support Ron's changes for hooking up ports.Kevin Lim
src/cpu/checker/cpu.hh: Now that BaseCPU is a MemObject, the checker must define this function. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch.hh: src/cpu/o3/iew.hh: src/cpu/o3/lsq.hh: src/cpu/o3/lsq_unit.hh: Implement getPort function so the connector can connect the ports properly. src/cpu/o3/fetch_impl.hh: src/cpu/o3/lsq_unit_impl.hh: The connector handles connecting the ports now. src/python/m5/objects/O3CPU.py: Add ports to the parameters. --HG-- extra : convert_revision : 0b1a216b9a5d0574e62165d7c6c242498104d918
2006-07-07Fix for bug when draining and a memory access is outstanding.Kevin Lim
--HG-- extra : convert_revision : 1af782cf023ae74c2a3ff9f7aefcea880bc87936
2006-07-07Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge --HG-- extra : convert_revision : e8933f852352164f4e50444f94cc6ee260e06766
2006-07-07Take the name of the checkpoint directory in when calling checkpoint() or ↵Kevin Lim
restoreCheckpoint(). src/sim/main.cc: src/sim/serialize.cc: src/sim/serialize.hh: Take in the directory name when checkpointing. --HG-- extra : convert_revision : 040e828622480f1051e2156f4439e24864c38d45
2006-07-07Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemKorey Sewell
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3 --HG-- extra : convert_revision : be8b295ebf54a7c6bf720a20ab6aa9f02aee8060
2006-07-07Fix address range calculation. Still need bus to handle snoop ranges.Ron Dreslinski
On the way towards multi-level caches (L2) src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: Fix address range calculation. Still need bus to handle snoop ranges. --HG-- extra : convert_revision : 800078d88aab5e563f4a9bb599f91cd44f36e625
2006-07-07Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemKorey Sewell
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3 --HG-- extra : convert_revision : f97469b7d19c82deb3d068f80546d729757c25e3
2006-07-07Minor fix for SMT Hello Worlds to finish correctly.Korey Sewell
Still, there is a problem with the LSQ and indexing out of range in the buffer. I havent nailed down the fix yet, but it's coming ... src/cpu/o3/commit_impl.hh: add space to DPRINT src/cpu/o3/cpu.cc: add newline to DPRINT src/cpu/o3/rob.hh: src/cpu/o3/rob_impl.hh: Each thread needs it's own squashedSeqNum for the case where they are both squashing at the same time and they dont write over each other's squash number. --HG-- extra : convert_revision : 2155421a8b5b20e4544eea3d3c53d3e715465fa6
2006-07-07Switch out fixes for CPUs.Kevin Lim
src/cpu/o3/cpu.cc: Fix up keeping proper state when switched out and drained. src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: Keep track of the event we use to schedule fetch initially and upon resume. We may have to cancel the event if the CPU is switched out. --HG-- extra : convert_revision : 60a2a1bd2cdc67bd53ca4a67aa77166c826a4c8c
2006-07-07Remove hack now that ports work properlyRon Dreslinski
--HG-- extra : convert_revision : 43c22294867d7cbbc67ae66ec41a1d1c89f5a59d
2006-07-07Update cpus to use the getPort function to use a connector object to connect ↵Ron Dreslinski
the I/D cache ports to memory configs/test/test.py: Update to use new cpu getPort functionality src/cpu/base.cc: Make cpu's a memObject to expose getPort interface src/cpu/base.hh: Make cpu's a memObject to export getPort interface src/cpu/simple/atomic.cc: src/cpu/simple/atomic.hh: src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: Now use the connector via getPort interface src/mem/cache/base_cache.cc: Make sure the cache recognizes all port names --HG-- extra : convert_revision : dbfefa978ec755bc8aa6f962ae158acf32dafe61
2006-07-07Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemKorey Sewell
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3 --HG-- extra : convert_revision : 90717b492139428e0c48be35a6bda45960c61086
2006-07-07Fix so that O3CPU doesnt segfault on exit.Korey Sewell
Major thing was to not execute commit if there are no active threads in CPU. src/cpu/o3/alpha/thread_context.hh: call deallocate instead of deallocateContext src/cpu/o3/commit_impl.hh: dont run commit stage if there are no instructions src/cpu/o3/cpu.cc: add deallocate event, deactivateThread function, and edit deallocateContext. src/cpu/o3/cpu.hh: add deallocate event and add optional delay to deallocateContext src/cpu/o3/thread_context.hh: optional delay for deallocate src/cpu/o3/thread_context_impl.hh: edit DPRINTFs to say Thread Context instead of Alpha TC src/cpu/thread_context.hh: optional delay src/sim/syscall_emul.hh: name stuff --HG-- extra : convert_revision : f4033e1f66b3043d30ad98dcc70d8b193dea70b6
2006-07-06Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge --HG-- extra : convert_revision : 942c43e2fdd68cde7aaaba5e88a667f80feab162
2006-07-06Be sure to call resume after restoring from a checkpoint.Kevin Lim
--HG-- extra : convert_revision : 4d672917038779a23f4ce7eb5d4e3039c1f5d726
2006-07-06Support serializing and unserializing in the O3 CPU. Also a few small fixes ↵Kevin Lim
for draining/switching CPUs. src/cpu/o3/commit_impl.hh: Fix to clear drainPending variable on call to resume. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: Support serializing and unserializing in the O3 CPU. src/cpu/o3/lsq_impl.hh: Be sure to say we have no stores to write back if the active thread list is empty. src/cpu/simple_thread.cc: src/cpu/simple_thread.hh: Slightly change how SimpleThread is used to copy from other ThreadContexts. --HG-- extra : convert_revision : 92a5109b3783a989d5b451036061ef82c56d3121
2006-07-06Fix the O3CPU to support the multi-pass method for checking if the system ↵Kevin Lim
has fully drained. src/cpu/o3/commit.hh: src/cpu/o3/commit_impl.hh: src/cpu/o3/decode.hh: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/rename.hh: src/cpu/o3/rename_impl.hh: Return a value so that the CPU can instantly return from draining if the pipeline is already drained. src/cpu/o3/cpu.cc: Use values returned from pipeline stages so that the CPU can instantly return from draining if the pipeline is already drained. --HG-- extra : convert_revision : d8ef6b811644ea67c8b40c4719273fa224105811
2006-07-06Various serialization changes to make it possible for the O3CPU to checkpoint.Kevin Lim
src/arch/alpha/regfile.hh: Define serialize/unserialize functions on MiscRegFile itself. src/cpu/o3/regfile.hh: Remove old commented code. src/cpu/simple_thread.cc: src/cpu/simple_thread.hh: Push common serialization code to ThreadState level. Also allow the SimpleThread to be used for checkpointing by other models. src/cpu/thread_state.cc: src/cpu/thread_state.hh: Move common serialization code into ThreadState. --HG-- extra : convert_revision : ef64ef515355437439af967eda2e610e8c1b658b
2006-07-06Timing cache works for hello world test.Ron Dreslinski
Still need 1) detailed CPU (blocking ability in cache) 1a) Multiple outstanding requests (need to keep track of times for events) 2)Multi-level support 3)MP coherece support 4)LL/SC support 5)Functional path needs to be correctly implemented (temporarily works without multiple outstanding requests (simple cpu)) src/cpu/simple/timing.cc: Temp hack because timing cpu doesn't export ports properly so single I/D cache communicates only through the Icache port. src/mem/cache/base_cache.cc: Handle marking MSHR's in service Add support for getting CSHR's src/mem/cache/base_cache.hh: Make these functions visible at the base cache level src/mem/cache/cache.hh: make the functions virtual src/mem/cache/cache_impl.hh: Rename the function to make sense src/mem/packet.hh: Accidentally clearing the needsResponse field when sending a response back. --HG-- extra : convert_revision : 2325d4e0b77e470fa9da91490317dc8ed88b17e2
2006-07-06Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem --HG-- extra : convert_revision : 7c7fc8a2f9579d443786e86dbcf906b355de69fc
2006-07-06Two minor FS compile fixes.Kevin Lim
src/dev/tsunami_pchip.hh: Need ULL() for 32-bit hosts. src/sim/pseudo_inst.cc: Forgot to remove sampler include from here. --HG-- extra : convert_revision : 6ab6bdc721290167b4c2b78da3d28a4992eb24d5
2006-07-06Fixes for draining.Kevin Lim
src/cpu/simple/timing.cc: Update for changed return values. src/python/m5/__init__.py: Loop in order to make sure all objects are really drained. Objects may become undrained as other objects become drained (e.g. a bus-bridge has a packet, while a bus is empty, and the first drain() will cause the bus-bridge to give the packet to the bus). The only case we know every object is actually drained is if they all return immediately that they are drained. --HG-- extra : convert_revision : 80057a1d6d30381bd0b67b23549bd202f447c5cb
2006-07-06Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem --HG-- extra : convert_revision : 507eefde3514c35ca8420408cc89590d83cc6fc6
2006-07-06Now timing reads work in single level of cache with simple cpuRon Dreslinski
src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.hh: Changes to handle timing reads in Simple CPU (blocking buffers) --HG-- extra : convert_revision : a2e7d4287d7cdfd1bbf9c929ecbeafde499a5b9f
2006-07-06Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge --HG-- extra : convert_revision : 0c4fbbe0826358a6a58f844bec34ce830ffd4ced
2006-07-06Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : 4669e87d29fa3e0ca9009f6b9dce72113220d7bc
2006-07-06Add default responder to busAli Saidi
Update configuration for new default responder on bus Update to devices to handle their own pci config space without pciconfigall Remove most of pciconfigall, it now is a dumbdevice which gets it's address based on the bus it's supposed to respond for Remove need for pci config space from platform, add registerPciDevice function to prevent more than one device from having same bus:dev:func and interrupt Remove pciconfigspace from pci devices, and py files Add calcConfigAddr that returns address for config space based on bus/dev/function + offset configs/test/fs.py: Update configuration for new default responder on bus src/dev/ide_ctrl.cc: src/dev/ide_ctrl.hh: src/dev/ns_gige.cc: src/dev/ns_gige.hh: src/dev/pcidev.cc: src/dev/pcidev.hh: Update to handle it's own pci config space without pciconfigall src/dev/io_device.cc: src/dev/io_device.hh: change naming for pio port break out recvTiming into two functions to reuse code src/dev/pciconfigall.cc: src/dev/pciconfigall.hh: removing most of pciconfigall, it now is a dumbdevice which gets it's address based on the bus it's supposed to respond for src/dev/pcireg.h: add a max size for PCI config space (per PCI spec) src/dev/platform.cc: src/dev/platform.hh: remove need for pci config space from platform, add registerPciDevice function to prevent more than one device from having same bus:dev:func and interrupt src/dev/sinic.cc: remove pciconfigspace as it's no longer a needed parameter src/dev/tsunami.cc: src/dev/tsunami.hh: src/dev/tsunami_pchip.cc: src/dev/tsunami_pchip.hh: add calcConfigAddr that returns address for config space based on bus/dev/function + offset (per PCI spec) src/mem/bus.cc: src/mem/bus.hh: src/python/m5/objects/Bus.py: add idea of default responder to bus src/python/m5/objects/Pci.py: add config port for pci devices add latency, bus and size parameters for pci config all (min is 8MB, max is 256MB see pci spec) --HG-- extra : convert_revision : 99db43b0a3a077f86611d6eaff6664a3885da7c9
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 13:08:57 +0000