summaryrefslogtreecommitdiff
AgeCommit message (Expand)Author
2018-06-21cpu: Fix bug introduced by RequestPtr type changeGiacomo Travaglini
2018-06-20base: Fix includes in AddrRangeMap header fileNikos Nikoleris
2018-06-20mem-cache: Fix TempCacheBlock insertJason Lowe-Power
2018-06-19mem: Use address range to find the right physical addressNikos Nikoleris
2018-06-19mem: Use address range to find the destination port in the xbarNikos Nikoleris
2018-06-19mem: Use the caching in the AddrRangeMap class in PhysicalMemoryGabe Black
2018-06-19mem: Use the caching built into AddrRangeMap in the xbarGabe Black
2018-06-19base: Build caching into the AddrRangeMap classGabe Black
2018-06-19base, mem: Disambiguate if an addr range is contained or overlapsNikos Nikoleris
2018-06-19mem-cache: Fix support for secure blocks in the FALRU cacheNikos Nikoleris
2018-06-15mem-cache: Initialize CacheBlk data pointerDaniel R. Carvalho
2018-06-15mem-cache: Forward declare ReplaceableEntryDaniel R. Carvalho
2018-06-15dev-arm: Fix the address range for some I/O devicesNikos Nikoleris
2018-06-15tests,style: add RISC-V assembly testsTuan Ta
2018-06-15sim: Add a SimObject python field which overrides the default c++ base.Gabe Black
2018-06-14cpu: Prevent suspended TimingSimple CPUs from fetching next instructionsTuan Ta
2018-06-14cpu: add a new instruction type 'Atomic'Tuan Ta
2018-06-14arch: support issuing Atomic Mem Operation (AMO) requestsTuan Ta
2018-06-14base,mem: Support AtomicOpFunctor in the classic memory systemTuan Ta
2018-06-14ruby: Revamp standalone SLICC scriptJason Lowe-Power
2018-06-14arch-arm: Adapting IllegalExecution fault for AArch32Giacomo Travaglini
2018-06-14arch-arm: Add Illegal Execution flag to PCStateGiacomo Travaglini
2018-06-14arch-arm: Read APSR in User ModeGiacomo Travaglini
2018-06-14system-arm: Split the VExpress_GEM5_V1 base dtsAndreas Sandberg
2018-06-14dev-arm: Add new VExpress_GEM5_V1_Base PlatformRohit Kurup
2018-06-14cpu-minor: Remove redundant thread startup callAndreas Sandberg
2018-06-14dev-arm: Remove deprecated GIC test interfacesAndreas Sandberg
2018-06-13tests: Make "UnitTest"s more like GTest so they can be in other dirs.Gabe Black
2018-06-13mem-cache: Remove unnecessary cast in SectorTags::findVictimNikos Nikoleris
2018-06-13arch-arm: Fix missing Request allocationGiacomo Travaglini
2018-06-13mem-cache: Insert on block allocationDaniel R. Carvalho
2018-06-13mem-cache: Make packet const in insertBlockDaniel R. Carvalho
2018-06-13mem-cache: Create Sector CacheDaniel R. Carvalho
2018-06-12tests: add some pthread and std::thread unit testsTuan Ta
2018-06-12ruby: Fix initial weight in weighted LRUDaniel R. Carvalho
2018-06-11misc: Using smart pointers for memory RequestsGiacomo Travaglini
2018-06-11misc: Substitute pointer to Request with aliased RequestPtrGiacomo Travaglini
2018-06-08mem-cache: Change Cache block tag checkDaniel R. Carvalho
2018-06-08mem-cache: Use secure bit in findVictimDaniel R. Carvalho
2018-06-08mem-cache: Move tagsInUse to childrenDaniel R. Carvalho
2018-06-08mem-cache: Return evictions along with victimsDaniel R. Carvalho
2018-06-08mem-cache: Use ReplaceableEntry in findBlockBySetAndWayDaniel R. Carvalho
2018-06-08sim: Rename the SimObject cxx_bases field to cxx_extra_bases.Gabe Black
2018-06-07dev-arm: Add a VirtIO MMIO device to VExpress_GEM5_V1Andreas Sandberg
2018-06-07dev-arm: Add a MMIO transport interface for VirtIOAndreas Sandberg
2018-06-07dev-arm: Add a GIC interrupt adaptorAndreas Sandberg
2018-06-06arch-arm: Remove dead doingStage2 variable in PT walkerAndreas Sandberg
2018-06-06system-arm: Update gem5 timer interrupt specificationAndreas Sandberg
2018-06-06arch-arm: Perform stage 2 lookups using the EL2 stateAndreas Sandberg
2018-06-06arch-arm: Respect EL from translation typeAndreas Sandberg
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 01:09:33 +0000