gem5 - gem5

Age	Commit message (Expand)	Author
2012-12-11	ruby: modify the directed tester to read/write streams	Nilay Vaish
2012-12-11	ruby: change slicc to allow for constructor args	Nilay Vaish
2012-12-11	ruby: add a prefetcher	Nilay Vaish
2012-12-11	ruby: add functions for computing next stride/page address	Nilay Vaish
2012-12-06	regression test: update a couple of config.ini files	Nilay Vaish
2012-12-06	TournamentBP: Fix some bugs with table sizes and counters	Erik Tomusk
2012-12-06	inorder cpu: add missing DPRINTF argument	Malek Musleh
2012-12-06	o3 cpu: remove some unused buggy functions in the lsq	Nathanael Premillieu
2012-11-19	config: Fix description of checkpoint option from cycle to tick	Andreas Hansson
2012-11-16	sim: have a curTick per eventq	Nilay Vaish
2012-11-10	regressions: stats update due to ruby functional access patch	Nilay Vaish
2012-11-10	ruby: support functional accesses in garnet flexible network	Nilay Vaish
2012-11-10	ruby: bug in functionalRead, revert recent changes	Nilay Vaish
2012-11-08	mem: Fix DRAM draining to ensure write queue is empty	Andreas Hansson
2012-11-03	x86, util: add m5_writefile to m5op_x86.S	Lluis Vilanova
2012-11-02	ruby: reset and dump stats along with reset of the system	Hamid Reza Khaleghzadeh ext:(%2C%20Lluc%20Alvarez%20%3Clluc.alvarez%40bsc.es%3E%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2012-11-02	mem: fix use after free issue in memories until 4-phase work complete.	Ali Saidi
2012-11-02	update stats for preceeding changes	Ali Saidi
2012-11-02	mem: Add support for writing back and flushing caches	Andreas Sandberg
2012-11-02	sim: Add drain methods to request additional cleanup operations	Andreas Sandberg
2012-11-02	sim: Add SWIG interface for Serializable	Andreas Sandberg
2012-11-02	python: Rename doDrain()->drain() and make it do the right thing	Andreas Sandberg
2012-11-02	sim: Reuse the code to change memory mode.	Andreas Sandberg
2012-11-02	sim: Move the draining interface into a separate base class	Andreas Sandberg
2012-11-02	cpu: O3 add a header declaring the DerivO3CPU	Andreas Sandberg
2012-11-02	cpu: Add header files for checker CPUs	Andreas Sandberg
2012-11-02	dev: Fix ethernet device inheritance structure	Andreas Sandberg
2012-11-02	sim: Include object header files in SWIG interfaces	Andreas Sandberg
2012-11-02	pci: Make Python wrapper cast to the right type	Andreas Sandberg
2012-11-02	mips: Remove unused Python file	Andreas Sandberg
2012-11-02	dev: Add missing inline declarations	Andreas Sandberg
2012-11-02	base: Add missing header file to addr_range.hh.	Andreas Sandberg
2012-10-09	m5: Expose m5 pseudo-instructions to C/C++ via a static library	James Clarkson
2012-11-02	ARM: dump stats and process info on context switches	Dam Sunwoo
2012-11-02	base: Fix a few incorrectly handled print format cases	Chander Sudanthi
2012-11-02	base: split out the VncServer into a VncInput and Server classes	Chander Sudanthi
2012-11-02	ISA: generic Linux thread info support	Dam Sunwoo
2012-11-02	sim: Fix as issue where exit events on instr queues are used after freed.	Ali Saidi
2012-11-02	o3: Fix a couple of issues with the local predictor.	Mrinmoy Ghosh
2012-11-02	Partly revert [4f54b0f229b5] and move draining to m5.changeToTiming	Andreas Sandberg
2012-10-31	mem: Fix typo in port comments	Andreas Hansson
2012-10-31	stats: Update stats for fixed simple-atomic-mp config	Andreas Hansson
2012-10-31	config: Fix a typo in the simple-atomic-mp configuration	Andreas Hansson
2012-10-30	stats: Update stats for unified cache configuration	Andreas Hansson
2012-10-30	config: Unify caches used in regressions and adjust L2 MSHRs	Andreas Hansson
2012-10-27	regressions: update stats for ruby fs test	Nilay Vaish
2012-10-27	ruby: set the is_icache param for caches	Malek Musleh
2012-10-27	Ruby: Use block size in configuring directory bits in address	Jason Power ext:(%2C%20Joel%20Hestness%20%3Chestness%40cs.wisc.edu%3E)
2012-10-26	config: Add a check for fastmem only used with Atomic CPU	Andreas Hansson
2012-10-26	config: Remove unused mem_size in fs.py	Andreas Hansson