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2012-01-28Merge with the main repo.Gabe Black
--HG-- rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
2012-01-27ns_gige: Fix a missing curly brace in if-statementAndreas Hansson
This patch adds a missing curly brace when clearing and setting the appropriate bits in the ns_gige.cc code. This commit is not based on any runtime bug experienced, but rather inspection of the code.
2012-01-26configs: actually add ARMv7a-like cpu/cache fileRonald Dreslinski
2012-01-26configs: A more realistic configuration of an ARM-like processorRonald Dreslinski
2012-01-25MEM: Fix fs.py by specifying the range size rather than endAndreas Hansson
This patch fixes the currently broken fs.py by specifying the size of the bridge range rather than the end address. This effectively subtracts one when determining the address range for the IO bridge (from IO bus to membus), and thus avoids the overlapping ranges.
2012-01-16Merge yet again with the main repository.Gabe Black
2012-01-12Fix memory corruption issue with CopyStringOut()Mitchell Hayenga
CopyStringOut() improperly indexed setting the null character, would result in zeroing a random byte of memory after(out of bounds) the character array.
2012-01-25stats: Update stats for final tick and memory bandwidth patchesAli Saidi
2012-01-25sim: display final value of curTick in statsAli Saidi
Different from sim_ticks in that this value is restored from checkpoints and is never reset. Useful for aligning with framebuffer output ticks
2012-01-25Mem: Add simple bandwidth stats to PhysicalMemoryAli Saidi
2012-01-23Config: Enable using O3 CPU and Ruby in SE modeNilay Vaish
2012-01-23O3, Ruby: Forward invalidations from Ruby to O3 CPUNilay Vaish
This patch implements the functionality for forwarding invalidations and replacements from the L1 cache of the Ruby memory system to the O3 CPU. The implementation adds a list of ports to RubyPort. Whenever a replacement or an invalidation is performed, the L1 cache forwards this to all the ports, which is the LSQ in case of the O3 CPU.
2012-01-23MemCmd: Add a command for invalidation requests to LSQNilay Vaish
This command will be sent from the memory system (Ruby) to the LSQ of an O3 CPU so that the LSQ, if it needs to, invalidates the address in the request packet.
2012-01-17MEM: Make the bus default port yet another portAndreas Hansson
This patch removes the idiosyncratic nature of the default bus port and makes it yet another port in the list of interfaces. Rather than having a specific pointer to the default port we merely track the identifier of this port. This change makes future port diversification easier and overall cleans up the bus code.
2012-01-17MEM: Removing the default port peer from Python portsAndreas Hansson
In preparation for the introduction of Master and Slave ports, this patch removes the default port parameter in the Python port and thus forces the argument list of the Port to contain only the description. The drawback at this point is that the config port and dma port of PCI and DMA devices have to be connected explicitly. This is key for future diversification as the pio and config port are slaves, but the dma port is a master.
2012-01-17MEM: Make the bus bridge unidirectional and fixed address rangeAndreas Hansson
This patch makes the bus bridge uni-directional and specialises the bus ports to be a master port and a slave port. This greatly simplifies the assumptions on both sides as either port only has to deal with requests or responses. The following patches introduce the notion of master and slave ports, and would not be possible without this split of responsibilities. In making the bridge unidirectional, the address range mechanism of the bridge is also changed. For the cases where communication is taking place both ways, an additional bridge is needed. This causes issues with the existing mechanism, as the busses cannot determine when to stop iterating the address updates from the two bridges. To avoid this issue, and also greatly simplify the specification, the bridge now has a fixed set of address ranges, specified at creation time.
2012-01-17MEM: Remove the functional ports from the memory systemWilliam Wang
The functional ports are no longer used and this patch cleans up the legacy that is still present in buses, memories, CPUs etc. Note that this does not refer to the class FunctionalPort (already removed), but rather ports with the name (and use) functional.
2012-01-17MEM: Separate queries for snooping and address rangesAndreas Hansson
This patch simplifies the address-range determination mechanism and also unifies the naming across ports and devices. It further splits the queries for determining if a port is snooping and what address ranges it responds to (aiming towards a separation of cache-maintenance ports and pure memory-mapped ports). Default behaviours are such that most ports do not have to define isSnooping, and master ports need not implement getAddrRanges.
2012-01-17MEM: Remove Port removeConn and MemObject deletePortRefsAndreas Hansson
Cleaning up and simplifying the ports and going towards a more strict elaboration-time creation and binding of the ports.
2012-01-17MEM: Remove the notion of the default portAndreas Hansson
This patch removes the default port and instead relies on the peer being set to NULL initially. The binding check (i.e. is a port connected or not) will eventually be moved to the init function of the modules.
2012-01-17MEM: Simplify ports by removing EventManagerAndreas Hansson
This patch removes the inheritance of EventManager from the ports and moves all responsibility for event queues to the owner. Eventually the event manager should be the interface block, which could either be the structural owner or a subblock like a LSQ in the O3 CPU for example.
2012-01-17CPU: Moving towards a more general port across CPU modelsAndreas Hansson
This patch performs minimal changes to move the instruction and data ports from specialised subclasses to the base CPU (to the largest degree possible). Ultimately it servers to make the CPU(s) have a well-defined interface to the memory sub-system.
2012-01-17MEM: Add port proxies instead of non-structural portsAndreas Hansson
Port proxies are used to replace non-structural ports, and thus enable all ports in the system to correspond to a structural entity. This has the advantage of accessing memory through the normal memory subsystem and thus allowing any constellation of distributed memories, address maps, etc. Most accesses are done through the "system port" that is used for loading binaries, debugging etc. For the entities that belong to the CPU, e.g. threads and thread contexts, they wrap the CPU data port in a port proxy. The following replacements are made: FunctionalPort > PortProxy TranslatingPort > SETranslatingPortProxy VirtualPort > FSTranslatingPortProxy --HG-- rename : src/mem/vport.cc => src/mem/fs_translating_port_proxy.cc rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
2012-01-17Ruby: Change the access permissions for MOESI hammerAndreas Hansson
Regression statistics update.
2012-01-17Ruby: Change the access permissions for MOESI hammerAndreas Hansson
This patch changes the access permission for the WB_E_W state from Busy to Read_Write to avoid having issues in follow-on patches with functional accesses going through Ruby. This change was made after consultation with all involved parties and is more of a work-around than a fix.
2012-01-17MEM: Add the system port as a central access pointAndreas Hansson
The system port is used as a globally reachable access point to the memory subsystem. The benefit of using an actual port is that the usual infrastructure is used to resolve any access and thus makes the overall system able to handle distributed memories in any configuration, and also makes the accesses agnostic to the address map. This patch only introduces the port and does not actually use it for anything.
2012-01-17MEM: Differentiate functional cache accesses from CPU and memoryAndreas Hansson
This patch changes the functionalAccess member function in the cache model such that it is aware of what port the access came from, i.e. if it came from the CPU side or from the memory side. By adding this information, it is possible to respect the 'forwardSnoops' flag for snooping requests coming from the memory side and not forward them. This fixes an outstanding issue with the IO bus getting accesses that have no valid destination port and also cleans up future changes to the bus model.
2012-01-16stats: undo parser change from initparam changeAli Saidi
2012-01-16Alpha: warn_once about broken PAL breakpoints.Steve Reinhardt
A recent changeset (aae12ce9f34c) removed support for PAL-mode breakpoints in Alpha, since it was awkward and likely unused. This patch lets a user know if they potentially run into this limitation.
2012-01-16debug: fix AllFlags::disable()Steve Reinhardt
Looks like copy-and-paste bug, apparently I'm the first person to ever use this since it's plainly broken.
2012-01-12inorder: MDU deadlock fixMaximilien Breughe
2012-01-12mips: compatibility between MIPS_SE and cross compiler from CodeSorceryDeyuan Guo
2012-01-12mips: Fix bugs in faults.cc/hh and tlb.cc for MIPS_FSDeyuan Guo
2012-01-12mips: Fix decoder of two float-convert instructionsDeyuan Guo
2012-01-12mips: definition of MIPS64_QNAN in registers.hhDeyuan Guo
2012-01-12PerfectCacheMemory: Remove references to CacheMsgNilay Vaish
The definition for the class CacheMsg was removed long back. Some declaration had still survived, which was recently removed. Since the PerfectCacheMemory class relied on this particular declaration, its absence let to compilation breaking down. Hence this patch.
2012-01-11Packet: Put back part of the assertAli Saidi
2012-01-11Packet: Remove meaningless assert statementAli Saidi
2012-01-11Ruby: Use map option for selecting b/w sparse and memory vectorNilay Vaish
2012-01-11Config: Add support for restoring using a timing CPUNilay Vaish
Currently there is an assumption that restoration from a checkpoint will happen by first restoring to an atomic CPU and then switching to a timing CPU. This patch adds support for directly restoring to a timing CPU. It adds a new option '--restore-with-cpu' which is used to specify the type of CPU to which the checkpoint should be restored to. It defaults to 'atomic' which was the case before.
2012-01-11Ruby: Resurrect Cache Warmup CapabilityNilay Vaish
This patch resurrects ruby's cache warmup capability. It essentially makes use of all the infrastructure that was added to the controllers, memories and the cache recorder.
2012-01-11Ruby Debug Flags: Remove one, add anotherNilay Vaish
The flag RubyStoreBuffer is being removed, instead RubySystem is being added
2012-01-11Ruby Port: Add a list of cpu ports attached to this portNilay Vaish
2012-01-11Ruby EventQueue: Remove unused functionsNilay Vaish
2012-01-11Ruby Sparse Memory: Add function for collating blocksNilay Vaish
This patch adds function to the Sparse Memory so that the blocks can be recorded in a cache trace. The blocks are added to the cache recorder which can later write them into a file.
2012-01-11Ruby: Add infrastructure for recording cache contentsNilay Vaish
This patch changes CacheRecorder, CacheMemory, CacheControllers so that the contents of a cache can be recorded for checkpointing purposes.
2012-01-11Ruby Memory Vector: Functions for collating and populating pagesNilay Vaish
This patch adds functions to the memory vector class that can be used for collating memory pages to raw trace and for populating pages from a raw trace.
2012-01-10Ruby: remove the files related to the tracerNilay Vaish
The Ruby Tracer is out of date with the changes that are being carried out to support checkpointing. Hence, it needs to be removed.
2012-01-10hgfilesize: skip files that have been removedNathan Binkert
2012-01-10MOESI Hammer: Update regression test outputNilay Vaish
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