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AgeCommit message (Expand)Author
2010-06-02ARM: Ignore attempts to disable coprocessors that aren't implemented anyway.Gabe Black
2010-06-02ARM: Implement the udiv instruction.Gabe Black
2010-06-02ARM: Implement the sdiv instruction.Gabe Black
2010-06-02ARM: Ignore writing a bad mode to CPSR with MSR.Gabe Black
2010-06-02ARM: Decode the CPS instruction.Gabe Black
2010-06-02ARM: Implement the CPS instruction.Gabe Black
2010-06-02ARM: Decode the SRS instruction.Gabe Black
2010-06-02ARM: Implement the SRS instruction.Gabe Black
2010-06-02ARM: Add a base class for SRS.Gabe Black
2010-06-02ARM: Implement a badMode function that says whether a mode is legal.Gabe Black
2010-06-02ARM: Allow flattening into any mode.Gabe Black
2010-06-02ARM: Decode TBB and TBH.Gabe Black
2010-06-02ARM: Decode the setend instruction.Gabe Black
2010-06-02ARM: Define the setend instruction.Gabe Black
2010-06-02ARM: Make a base class for instructions that use only an immediate.Gabe Black
2010-06-02ARM: Decode the arm version of ldrexd.Gabe Black
2010-06-02ARM: Decode the strex instructions.Gabe Black
2010-06-02ARM: Implement the strex instructions.Gabe Black
2010-06-02ARM: Set CPSR.E to SCTLR.EE on faults.Gabe Black
2010-06-02ARM: Warn about not implementing MPU translation, not panic about MMU.Gabe Black
2010-06-02ARM: Ignore/warn on accesses to the DRBAR, DRACR, and DRSR registers.Gabe Black
2010-06-02ARM: Allow access to the RGNR register.Gabe Black
2010-06-02ARM: Make the MPUIR register report that 1 unified data region is supported.Gabe Black
2010-06-02ARM: Ignore/warn on accesses to the BPIALLIS and BPIALL registers.Gabe Black
2010-06-02ARM: Respect the E bit of the CPSR when doing loads and stores.Gabe Black
2010-06-02ARM: Zero the micropc when vectoring to a fault.Gabe Black
2010-06-02ARM: Implement the V7 version of alignment checking.Gabe Black
2010-06-02ARM: Decode the RFE instruction.Gabe Black
2010-06-02ARM: Implement the RFE instruction.Gabe Black
2010-06-02ARM: Add a base class for the RFE instruction.Gabe Black
2010-06-02ARM: Make sure some undefined thumb32 instructions fault.Gabe Black
2010-06-02ARM: Squash the low order bits of the PC when performing a regular branch.Gabe Black
2010-06-02ARM: When changing the CPSR and branching, make sure the branch is second.Gabe Black
2010-06-02ARM: Ignore/warn when CSSELR or CCSIDR are accessed.Gabe Black
2010-06-02ARM: Ignore/warn access to the bpimva registers.Gabe Black
2010-06-02ARM: Ignore/warn on accesses to the dccmvac register.Gabe Black
2010-06-02ARM: Decode the enterx and leavex instructions.Gabe Black
2010-06-02ARM: Implement the enterx and leavex instructions.Gabe Black
2010-06-02ARM: Fix the implementation of BX to work in thumbEE mode.Gabe Black
2010-06-02ARM: When an instruction is intentionally undefined, fault on it.Gabe Black
2010-06-02ARM: Decode the thumb version of the ldrd and strd instructions.Gabe Black
2010-06-02ARM: Explicitly keep track of the second destination for double loads/stores.Gabe Black
2010-06-02ARM: Decode the thumb32 load byte/memory hint instructions.Gabe Black
2010-06-02ARM: Decode the load halfword, memory hints instructions for 32 bit Thumb.Gabe Black
2010-06-02ARM: Ignore/warn on accesses to icimvau.Gabe Black
2010-06-02ARM: Ignore/warn on iciallu.Gabe Black
2010-06-02ARM: Ignore/warn on ICIALLUIS.Gabe Black
2010-06-02ARM: Add support for the clidr register.Gabe Black
2010-06-02ARM: Decode the unimplemented data barrier CP15 accesses.Gabe Black
2010-06-02ARM: Implement a stub of CPACR.Gabe Black