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AgeCommit message (Expand)Author
2012-03-23Ruby: Fix Set::print for 32-bit hostsAndreas Hansson
2012-03-22MEM: Unify bus access methods and prepare for master/slave splitAndreas Hansson
2012-03-22MEM: Split SimpleTimingPort into PacketQueue and portsAndreas Hansson
2012-03-22Scons: Remove Werror=False in SConscript filesAndreas Hansson
2012-03-21Python: Fix a conditional expression that requires Python 2.5Andreas Hansson
2012-03-21ARM: Update stats for IT and conditional branch changesAli Saidi
2012-03-21ARM: Fix case where cond/uncond control is mis-specifiedNathanael Premillieu
2012-03-21ARM: Clean up condCodes in IT blocks.Ali Saidi
2012-03-21ARM: IT doesn't need to be serializing.Geoffrey Blake
2012-03-21O3: Fix sizing of decode to rename skid buffer.Andrew Lukefahr
2012-03-21ARM: Add RTC to PBX SystemKoan-Sin Tan
2012-03-21O3: Fix size of skid buffer between fetch and decode when widths are differentBrian Grayson
2012-03-21ARM: Fix uninitialized value in ARM RTC model.Ali Saidi
2012-03-19Garnet: Stats at vnet granularity + code cleanupTushar Krishna
2012-03-19gcc: Clean-up of non-C++0x compliant code, first stepsAndreas Hansson
2012-03-19clang: Fix recently introduced clang compilation errorsAndreas Hansson
2012-03-19scripts: Fix to ensure that port connection count is always setAndreas Hansson
2012-03-16ruby_fs.py: Add call to createInterruptController()Nilay Vaish
2012-03-16FSConfig.py: fix a typo makeLinuxAlphaRubySystemNilay Vaish
2012-03-16build: remove implicit-cache setting of scons from recent build faster patchMarc Orr
2012-03-11se.py: Changes to ruby portion due to SE/FS mergeNilay Vaish
2012-03-11O3: Add fatal when fetchWidth > Impl::MaxWidth.Brian Grayson
2012-03-09ARM: Fix memory starting at non-zero address and exceeding max mem for a system.Ali Saidi
2012-03-09ARM: Update stats for CBNZ fix.Ali Saidi
2012-03-09ARM: Fix branch prediction issue with CB(N)Z instructionBrian Grayson
2012-03-09ARM: Update stats for valgrind fix and replace config.inis which are out of d...Ali Saidi
2012-03-09O3/Ozone: Eliminate dead code counting software prefetch instsGeoffrey Blake
2012-03-09CheckerCPU: Make some basic regression tests for CheckerCPUGeoffrey Blake
2012-03-09CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPUGeoffrey Blake
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
2012-03-09ARM: Don't reset CPUs that are going to be switched in.Ali Saidi
2012-03-09System: Move code in initState() back into constructor whenever possible.Ali Saidi
2012-03-09ARM: Fix valgrind reported error on O3 that was causing minor stats changes.Ali Saidi
2012-03-09cache: Allow main memory to be at disjoint address ranges.Ali Saidi
2012-03-08Fix the SPARC fs regression by adding a call to createInterruptController.Gabe Black
2012-03-06build scripts: Made minor modifications to reduce build overhead time.Marc Orr
2012-03-06Stats: Update stats for changeset 8868Andreas Hansson
2012-03-02SConstruct: rename and document AddM5OptionSteve Reinhardt
2012-03-02SConstruct: update comments & doc stringsSteve Reinhardt
2012-03-02DynInst: get rid of dead MyHash code.Steve Reinhardt
2012-03-02CPU: Check that the interrupt controller is created when neededAndreas Hansson
2012-03-02Stats: Fix the realview regression stats after nvmem moveAndreas Hansson
2012-03-02Ruby: Rename RubyPort::sendTiming to avoid overriding base classAndreas Hansson
2012-03-02ARM: FIx a bug preventing multiple cores booting a VExpress_EMM machine.Ali Saidi
2012-03-01ARM: FIx missing cf controller connection.Ali Saidi
2012-03-01VNC: spacingChander Sudanthi
2012-03-01ARM: Add support for Versatile Express extended memory mapAli Saidi
2012-03-01ARM: Add RTC device for ARM platforms.Ali Saidi
2012-03-01ARM: Add limited CP14 support.Matt Horsnell
2012-03-01Cache: Fix an issue with LRU when bonus block is used to complete transaction.Ali Saidi