summaryrefslogtreecommitdiff
AgeCommit message (Expand)Author
2019-04-08learning_gem5,configs: Update ruby_testJason Lowe-Power
2019-04-08learning_gem5: Fix vector port panic in SimpleCacheJason Lowe-Power
2019-04-08configs: Fix import path error in learning_gem5 part3Jason Lowe-Power
2019-04-08configs: Add full path for learning_gem5 binariesJason Lowe-Power
2019-04-08configs: Removed redudant exec-style importRyan Gambord
2019-04-06mem: Add a MemBackdoor type to track memory backdoors.Gabe Black
2019-04-05cpu: Correctly account for executed instructions in simple cpusNikos Nikoleris
2019-04-05mem-cache: ambiguous use of abs functionRyan Gambord
2019-04-05mem: Reverse order of write/read mem queue checkJason Lowe-Power
2019-04-05tests: Add Jenkins presubmit and continuous test scriptsJason Lowe-Power
2019-04-04mem-cache: AMPM Prefetcher fails when restoring from a checkpointJavier Bueno
2019-04-03misc: Removed inconsistency in O3* debug msgsAndrea Mondelli
2019-04-03arch-mips: added missing override specifier (o3)Andrea Mondelli
2019-04-03mem-cache: Fix PIF prefetcher compilation error with NULL ISAJavier Bueno
2019-04-03mem-cache: ISB prefetcher was triggering an assertionJavier Bueno
2019-04-03mem-cache: Fix panic in Indirect Memory prefetcherJavier Bueno
2019-04-02dev-arm: Make GICv3 maintenance interrupt an ArmInterruptGiacomo Travaglini
2019-04-02mem-cache: Proactive Instruction Fetch ImplementationIvan Pizarro
2019-04-01dev-arm: Correct cast of template parameterAndrea Mondelli
2019-03-29systemc: Templatize the gem5/TLM bridge SimObjects.Gabe Black
2019-03-29systemc: Delete extra code from src/systemc/tlm_bridge.Gabe Black
2019-03-29systemc: Create unified gem5/TLM bridge SimObjects.Gabe Black
2019-03-29tlm: Initial import of tlm/gem5 bridge code.Gabe Black
2019-03-29systemc: Provide a utility Port TLM socket wrapper class.Gabe Black
2019-03-28cpu: Added a probe to notify the address of retired instructionsJavier Bueno
2019-03-28mem-cache: Remove extra cache header from AMAPDaniel R. Carvalho
2019-03-28arch-arm: Fix use of bitwise operators on booleansJavier Setoain
2019-03-28arch-arm: Fix index generation for VecElem operandsGiacomo Travaglini
2019-03-27dev-arm: Rename GIC maintenance interrupt from ppint to maint_intGiacomo Travaglini
2019-03-27dev-arm: Fix GICv3 overflow for INTID > 256Giacomo Travaglini
2019-03-27dev-arm: Writing ICENABLER for non-SPIs is RAZ/WI (or RES0)Giacomo Travaglini
2019-03-27config: Use the corresponding HPI Caches when using the HPI cpuJavier Bueno
2019-03-27cpu: Fixed the indirect branch predictor GHR handlingPau Cabre
2019-03-26mem: Deleting this init() method was accidentally dropped during rebase.Gabe Black
2019-03-26mem: Clean up the xbars a little.Gabe Black
2019-03-26base: Make AddrRangeMap able to return non-const iterators.Gabe Black
2019-03-26configs: fix class reference in CacheConfigsJavier Bueno
2019-03-26dev-arm: Set/Unset dma coherent mode from pythonGiacomo Travaglini
2019-03-26base,python: Fix to allow multiple --debug-ignore values.Isaac Sánchez Barrera
2019-03-25configs: Remove default kernel value from system creationDaniel R. Carvalho
2019-03-25arch-arm: Add missing fall-through defaultsJavier Setoain
2019-03-25arch-power: Rename program counter registersSandipan Das
2019-03-25arch-power: Simplify doubleword operand typesSandipan Das
2019-03-23misc: missing override specifierAndrea Mondelli
2019-03-22sim-se: Fixed initialization array sizeTiago Muck
2019-03-22base: Fix CircularQueue's operator-= when negative subtractionGiacomo Travaglini
2019-03-22base: Fix CircularQueue when diffing iteratorsGiacomo Travaglini
2019-03-21dev-arm: ambiguous use of getPort()Andrea Mondelli
2019-03-21tests: Add ignore for stdin not terminalJason Lowe-Power
2019-03-21tests: Use full path for DownloadedProgramJason Lowe-Power