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2019-04-08learning_gem5,configs: Update ruby_testJason Lowe-Power
Use SimpleMemory instead of DDR3 so we can use the timing results in tests. By using SimpleMemory, even if the DRAM timing changes the timing of this test won't change. I expect the timing of SimpleMemory to never change. Change-Id: I4c75981d7b8bfc4dcca59e628e89f5a6ea4c0e36 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17871 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-04-08learning_gem5: Fix vector port panic in SimpleCacheJason Lowe-Power
Change-Id: I0f3b71fdbed77690c533d9d14e774ab2cc08c053 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17870 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-04-08configs: Fix import path error in learning_gem5 part3Jason Lowe-Power
Change-Id: I2c5cd22bded998bae8e7aa77e42e1b042ce1c5f5 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17869 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-04-08configs: Add full path for learning_gem5 binariesJason Lowe-Power
Change-Id: Ie48429d65e322136109a223ed404937989aae494 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17868 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-04-08configs: Removed redudant exec-style importRyan Gambord
garnet_synth_traffic.py imports common.Options on line 40, so exec'ing the Options.py file again seems redundant. It also runs Options.py as a script rather than a module, which throws ValueError: Attempted relative import in non-package due to the recent change to python3 imports. Change-Id: Id729a8dfa776af0d14312e765168aff6900eb727 Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17888 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-04-06mem: Add a MemBackdoor type to track memory backdoors.Gabe Black
These are similar to the structures TLM's DMI mechanism uses. Instead of having an invalidation broadcast which propogates backwards up the port hierarchy, this mechanism tracks a set of callbacks which are triggered when a back door is invalidated to let other holders clean up their bookkeeping. Change-Id: If24489258dcaee14d7b6e5b996dfb1c2636f26ab Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17589 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-04-05cpu: Correctly account for executed instructions in simple cpusNikos Nikoleris
Change-Id: I53f34b2d9db6e4d2e03dde42a970764bb2a5e701 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17730 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-04-05mem-cache: ambiguous use of abs functionRyan Gambord
std::abs doesn't accept unsigned long long, generating the error: error: call to 'abs' is ambiguous Use instead a compare-and-subtract idiom. Also, Changed return type of distanceFromTrigger from unsigned int to Addr to prevent overflow problems. Change-Id: Ia7752c1c7a838f98e8c7ed6ade9f586f31bbcf7d Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17788 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-05mem: Reverse order of write/read mem queue checkJason Lowe-Power
For atomic RMW instructions that go directly to memory, we want to put them on the write queue instead of the read queue. Swap the if/else condition to accomplish this. Note: This is ignoring the read latency of the RMW, but these instructions should usually be handled in caches anyway. Change-Id: I62dbfff3a16ac470f1ebdb489abe878962b20bb6 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17828 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-05tests: Add Jenkins presubmit and continuous test scriptsJason Lowe-Power
Note that continuous currently isn't used. Change-Id: Ifcff88c8c4c75a9f630b97eaca22edd1681529c3 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17456 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-04-04mem-cache: AMPM Prefetcher fails when restoring from a checkpointJavier Bueno
The preriodic event triggers an assertion due to an incorrect tick value to schedule when restoring from a checkpoint. Change-Id: I9454dd0c97d5a098f8a409886e63f7a7e990947c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17732 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-03misc: Removed inconsistency in O3* debug msgsAndrea Mondelli
Added consistency in the DEBUG message form, to allow a better parsing. Fixed sn/tid type parameter. Removed some annoying newlines Change-Id: I4761c49fc12b874a7d8b46779475b606865cad4b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17248 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-04-03arch-mips: added missing override specifier (o3)Andrea Mondelli
Change-Id: Ic538825a2964fd62def672b933a83067a15bd12a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17648 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-04-03mem-cache: Fix PIF prefetcher compilation error with NULL ISAJavier Bueno
Referencing BaseCPU is causing a compilation error when using the NULL ISA. This patch changes the reference to a SimObject, which fixes the problem. Change-Id: I2530486cab65974f5b83e54a733c4b0e98730d26 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17731 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-03mem-cache: ISB prefetcher was triggering an assertionJavier Bueno
An assertion ignored the case when an entry of the SP table had been invalidated. Change-Id: I5bf04e7a0979300b0f41f680c371f6397d4cbf3f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17734 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-03mem-cache: Fix panic in Indirect Memory prefetcherJavier Bueno
Memory requests with a size non-power-of-two and less than 8 values were causing a panic, but there these should be allowed and ignored by the prefetcher. Change-Id: I86baa60058cc8a7f232d6ba5748d4c24a463c840 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17733 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-02dev-arm: Make GICv3 maintenance interrupt an ArmInterruptGiacomo Travaglini
Change-Id: I88e2b72849cdf3f69026c62517303837e7d3d551 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17629 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-04-02mem-cache: Proactive Instruction Fetch ImplementationIvan Pizarro
Ferdman, M., Kaynak, C., & Falsafi, B. (2011, December). Proactive instruction fetch. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (pp. 152-162). ACM. Change-Id: I38c3ab30a94ab279f03e3d5936ce8ed118310c0e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16968 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-01dev-arm: Correct cast of template parameterAndrea Mondelli
Clang with -Wconstant-conversion is _very_ restrictive on casting. The shift operator results in an incorrect promotion. This patch add a compile-time static cast that remove the error when clang is used. Change-Id: I3aa1e77da2565799feadc32317d5faa111b2de86 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17308 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-29systemc: Templatize the gem5/TLM bridge SimObjects.Gabe Black
The C++ side is templated, and there are python versions for each (currently two) width of bridge supported. Change-Id: I4baa9f22d4c87629d45e9e1292eb66c65d25a655 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17234 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-29systemc: Delete extra code from src/systemc/tlm_bridge.Gabe Black
Much of the code in src/systemc/tlm_bridge has been absorbed into the TLM/gem5 bridge SimObjects and is no longer needed and redundant with the original version in util/. Change-Id: I0fa7af67649987cf9f6fc5cd4783002dde2242ac Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17233 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-29systemc: Create unified gem5/TLM bridge SimObjects.Gabe Black
These objects expose a standard TLM initiator or target socket with width 64, and a gem5 slave or master port. What goes in one type of port comes out the other with the appropriate conversion applied. Change-Id: I65e07f746d46d3db0197968b78fffc5ddaede9bf Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17232 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-29tlm: Initial import of tlm/gem5 bridge code.Gabe Black
This is a slightly mangled version of the existing bridge code in util/tlm/src/. The changes fix some small style issues, change to gem5 specific include paths, and removes the Gem5SimControl code. That code coordinates gem5 with the external systemc kernel, and in this usage there's no external kernel. The code imported here compiles, but it isn't yet expected to work. Change-Id: I9c593a52e2554534720d21cd31a03e543ad897ad Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17231 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-29systemc: Provide a utility Port TLM socket wrapper class.Gabe Black
This class should make it easy to attach TLM sockets into the gem5 python Port config mechanism. Change-Id: I3548c654d56bfc852f3fc98fe6433163b14f7fe3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17230 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-28cpu: Added a probe to notify the address of retired instructionsJavier Bueno
A probe is added to notify the address of each retired instruction. Change-Id: Iefc1b09d74b3aa0aa5773b17ba637bf51f5a59c9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17632 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-28mem-cache: Remove extra cache header from AMAPDaniel R. Carvalho
The cache header was being included in the AMAP, although not used, which resulted in slightly longer compilation time. Change-Id: I3654bc719c6b5f558af116addae159301602a3cf Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17711 Reviewed-by: Javier Bueno Hedo <javier.bueno@metempsy.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-28arch-arm: Fix use of bitwise operators on booleansJavier Setoain
Change-Id: I3762b2921f1d00a9104d8dc11a19dc0a219581e5 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17288 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-28arch-arm: Fix index generation for VecElem operandsGiacomo Travaglini
Current operand generation is not providing VecElems with the right vector index and element index. The bug was covered when registers were 128 bit wide, but with SVE we have augmented the vector register size and the bug has been exposed. E.g. With dest = 2, FpDestP2 = (vec_index = 0, elem_index = 4) whereas it should be FpDestP2 = (vec_index = 1, elem_index = 0) Change-Id: Iad02fb477afd0d3dd3d437bf2ca4338fbd142107 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17710
2019-03-27dev-arm: Rename GIC maintenance interrupt from ppint to maint_intGiacomo Travaglini
ppint is a generic name which only reflects Arm recommendation of assigning the maintanance interrupt to a PPI (numbered 25) Change-Id: Ic5abb6ed50817ad2d165b5df46dd989eb195a9db Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17628 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-27dev-arm: Fix GICv3 overflow for INTID > 256Giacomo Travaglini
SPIs can get to a maximum number of 1023, so that an uint8_t is not capable of representing all of them. Change-Id: I7a2c43b41ac93eabdfcf8311681240416b954177 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17631 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-27dev-arm: Writing ICENABLER for non-SPIs is RAZ/WI (or RES0)Giacomo Travaglini
For SGIs and PPIs: * When ARE is 1 (only value supported in gem5) for the Security state of an interrupt, the field for that interrupt is RES0 and an implementation is permitted to make the field RAZ/WI in this case. Change-Id: I6da2a89b1c848d458f42540e0113e7139b910abb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17630 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-27config: Use the corresponding HPI Caches when using the HPI cpuJavier Bueno
The HPI cpu comes with specific cache definitions, but they are ignored when using this cpu. This patch solves this in the same way it is done for the O3_ARM_v7a cpu. Change-Id: Iabf763291099d9508e3c5eac00b1e233cb38ce6b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17708 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-27cpu: Fixed the indirect branch predictor GHR handlingPau Cabre
The internal indirect predictor global history was not being updated properly, resulting in higher than expected miss rates Also added a parameter to set the size of the indirect predictor GHR Change-Id: Ibc797816974cba6719da65122801e8919559a003 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reported-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16928 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andrea Mondelli <Andrea.Mondelli@ucf.edu> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-26mem: Deleting this init() method was accidentally dropped during rebase.Gabe Black
Deleting this init() method was part of a change just committed, but was accidentally dropped during a rebase. Change-Id: I0f22778596ed11e182f3111d9999a0fef727f6cc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17688 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-26mem: Clean up the xbars a little.Gabe Black
Get rid of comments which just restate the code, get rid of redundant "virtual" keywords, add "override"s, fix style, and get rid of xbar::init which was empty and hiding the parent class init. Change-Id: I8ce20abee340baa88084d142f2fb8c633ee54ba9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17592 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-26base: Make AddrRangeMap able to return non-const iterators.Gabe Black
The erase() method only accepts regular iterators which is consistent with the normal STL map, but the existing find() only returns const iterators. The STL container can return either depending on if "this" is const. Unfortunately there isn't a great way to have only one find implementation which returns the right type of iterator under the right conditions. Also, it's not possible to turn a const_iterator into an iterator, but it is possible to go the other way. This change duplicates very short functions which return iterators, and for find does the only thing I could find which avoids having to copy that whole large function. Change-Id: I2f789b5d0881feb9adff9978bd40e31731c6a688 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17588 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-26configs: fix class reference in CacheConfigsJavier Bueno
One reference was not properly updated when changing to absolute import paths Change-Id: Idf330487d5d08d92ebb4489f16d75429f882bd7a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17541 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-26dev-arm: Set/Unset dma coherent mode from pythonGiacomo Travaglini
With this patch it will be possible to automatically enable/disable the dma-coherent property for the GenericArmPciHost autogenerated DTB. This has been done by adding the _dma_coherent param. Change-Id: I1759fced74e42410462637ca77997a351314a90a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16748 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-26base,python: Fix to allow multiple --debug-ignore values.Isaac Sánchez Barrera
When adding multiple SimObjects to --debug-ignore, either separating the values with a colon or adding multiple --debug-ignore flags, the previous code only ignored the last SimObject in the list. This changeset adds and uses new `ObjectMatch::add` and `Logger::addIgnore` methods to make the functionality of the flag consistent with its description. Change-Id: Ib6967a48611ea59a211f81af2a970c4de429b1be Signed-off-by: Isaac Sánchez Barrera <isaac.sanchez@bsc.es> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17488 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-25configs: Remove default kernel value from system creationDaniel R. Carvalho
Kernel was being set using a placeholder and then assigned the correct value. This would generate the following error if the placeholder file did not exist: 'IOError: Can't find file <placeholder> on path' This patch follows the same directions of commit 12eca7ac04ae1ba559bf322b5c625513929d369d and removes the default values, forcing the user to properly configure the kernel. Change-Id: I0eb45d12eda6b6efe9a3fe118996b640844a7b34 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11850 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-25arch-arm: Add missing fall-through defaultsJavier Setoain
Change-Id: Ie64b83d754c4719a77c7788879be71304a9b786e Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17289 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andrea Mondelli <Andrea.Mondelli@ucf.edu> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-03-25arch-power: Rename program counter registersSandipan Das
The Power ISA specification lists the Program Counter (PC) and the Next Program Counter (NPC) registers as Current Instruction Address (CIA) and Next Instruction Address (NIA). This applies the ISA naming convention for these two registers. Change-Id: I8b9094ab1c809f4dfdb4d7330c17f360adf063e9 Signed-off-by: Sandipan Das <sandipan@linux.ibm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16603 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-25arch-power: Simplify doubleword operand typesSandipan Das
Currently, 'sq' and 'uq' are used to represent signed and unsigned doublewords respectively. Since all recent Power ISA specifications list 128-bit quadwords as a valid data type, it may be misleading to use the current terminology in case support for such operands are added in the future. So, to simplify this, 'sd' and 'ud' are used to represent signed and unsigned doublewords respectively. Change-Id: Ie7831c596fc8f9ddfdf3b652c37cfe26484ebe01 Signed-off-by: Sandipan Das <sandipan@linux.ibm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16602 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-23misc: missing override specifierAndrea Mondelli
Missing specifier of overridden virtual function declared in sim_object.hh Removed redundant "virtual" keyword Change-Id: I42aa3349b537c9e62607bce20cf1b3aabdb99bf2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17468 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-22sim-se: Fixed initialization array sizeTiago Muck
Doubled the size of the zeroed auxiliary vector since 2 * intSize on aarch64 > sizeof(uint64). Change-Id: I5196b000a696e9ea3f2b5daa5d5bb071794369aa Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17088 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-03-22base: Fix CircularQueue's operator-= when negative subtractionGiacomo Travaglini
Using operator-= when the rhs is a negative value is equivalent to using += on -rhs. This is fixing rounding in that scenario. Change-Id: Ia22e51f81a6805d27fd6b2115d288bb23421d00f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17528 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-22base: Fix CircularQueue when diffing iteratorsGiacomo Travaglini
This patch is fixing CircularQueue iterators' subtraction, in particular the behaviour when head and tail round multiple times. Change-Id: Ie79ac8accd30a10cf039cf4def87675b01375d6b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17188 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-21dev-arm: ambiguous use of getPort()Andrea Mondelli
The recent introduction of getPort() creates a conflict with the existing method used in arm MMU. This patch rename the old getPort() in getDMAPort() according to the returned value (DmaPort class type) Change-Id: Ief3d83650fd6b08490522341631244be06e380ce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17469 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-21tests: Add ignore for stdin not terminalJason Lowe-Power
Change-Id: I496a9f3a0156557415d455dd2ca54c92577ca5f5 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17455 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-21tests: Use full path for DownloadedProgramJason Lowe-Power
Change-Id: I1dceca80a425293d64f81b06ddff499363f18bc0 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17454 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-08 20:31:26 +0000