summaryrefslogtreecommitdiff
AgeCommit message (Expand)Author
2007-05-31Early micro assemblerGabe Black
2007-05-31x86 work that hadn't been checked in.Gabe Black
2007-05-30Fix cut-n-pasto to make the path correctNathan Binkert
2007-05-30Fix compiling on Solaris since Nate's libelf changeAli Saidi
2007-05-30tport.cc:Steve Reinhardt
2007-05-29A little more cleanup & refactoring of SimpleTimingPort.Steve Reinhardt
2007-05-28Merge zizzer.eecs.umich.edu:/bk/newmemSteve Reinhardt
2007-05-28Fix M4 command line... wasn't working on zizzer.Steve Reinhardt
2007-05-28Restructure SimpleTimingPort a bit:Steve Reinhardt
2007-05-28Reformat comments to meet line length restriction.Steve Reinhardt
2007-05-28Remove unnecessary include of physical.hh.Steve Reinhardt
2007-05-27Move SimObject python files alongside the C++ and fixNathan Binkert
2007-05-26Get rid of GNU libelf and its autoconf nastiness and replaceNathan Binkert
2007-05-25Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2007-05-25Make the lexer and parser use objects and not the last lexer and parser gener...Gabe Black
2007-05-24Update to ply 2.3Nathan Binkert
2007-05-22memtest.py:Steve Reinhardt
2007-05-21Change getDeviceAddressRanges to use bool for snoop arg.Steve Reinhardt
2007-05-20Add new EventWrapper constructor that takes a Tick valueSteve Reinhardt
2007-05-20Insist that PhysicalMemory object have at least one connection.Steve Reinhardt
2007-05-19Oops... some places in C++ explicitly ask for a "functional"Steve Reinhardt
2007-05-19PhysicalMemory has vector of uniform ports instead of one special one.Steve Reinhardt
2007-05-18Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2007-05-18Changes to make simple cpu handle pcs appropriately for x86Gabe Black
2007-05-16Update the release notes for the 2.0 beta 3 releaseNathan Binkert
2007-05-15update all the regresstion tests for releaseAli Saidi
2007-05-15Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemAli Saidi
2007-05-15Merge zizzer:/bk/newmemAli Saidi
2007-05-15add an l2 cache option to se example configAli Saidi
2007-05-15hopefully the final hacky change to make the bus bridge work okAli Saidi
2007-05-14Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2007-05-14Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemAli Saidi
2007-05-14Merge zizzer:/bk/newmemAli Saidi
2007-05-14couple more bug fixes for intel nicAli Saidi
2007-05-14add uglyiness to fix dmasAli Saidi
2007-05-13Eliminate unused PacketPtr from BaseCache'sSteve Reinhardt
2007-05-13Split BaseCache::CacheEvent into RequestEvent and ResponseEvent.Steve Reinhardt
2007-05-13Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemAli Saidi
2007-05-13fix handling of atomic packetsAli Saidi
2007-05-11Move full CPU sim object stuff into the encumbered directoryNathan Binkert
2007-05-11Float should have a c++ param typeNathan Binkert
2007-05-11total should be the sum of the vector result of an operation,Nathan Binkert
2007-05-10remove hit_latency and make latency do the right thingAli Saidi
2007-05-10Merge zizzer:/bk/newmemAli Saidi
2007-05-10update for bus bridge updatesAli Saidi
2007-05-10add/update parameters for bus bridgeAli Saidi
2007-05-09couple of updates in the intel nicAli Saidi
2007-05-09update for new reschedule semanticsAli Saidi
2007-05-09undo my previous bus change, it can make the bus deadlock.. so it still const...Ali Saidi
2007-05-09Merge zeep:/z/saidi/work/m5.newmemAli Saidi
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 13:28:29 +0000