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AgeCommit message (Expand)Author
2006-10-26Changed the number of register windows to be more realistic.Gabe Black
2006-10-26Got rid of some debug outputGabe Black
2006-10-26Change the default function from setMiscRegWithEffect to setMiscRegGabe Black
2006-10-25Fixed the priv instruction format.Gabe Black
2006-10-25Implemented the saved and restored instructions, fixed up register window ins...Gabe Black
2006-10-25Fixed the bitfield FCN to include the right bits.Gabe Black
2006-10-25Implemented the SPARC fill and spill handlers.Gabe Black
2006-10-24Replace the Alpha No op with a SPARC one.Gabe Black
2006-10-23Minor compile fix. Not sure why this is broken.Gabe Black
2006-10-23Move around more SPARC memory code, and make block memory operations work wit...Gabe Black
2006-10-23Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2006-10-23Add reference outputs for SPARC on the atomic timing cpu modelGabe Black
2006-10-23Broke Load/Store instructions into microcode, and partially refactored memory...Gabe Black
2006-10-23Don't let interupts interupt microcode at undesired points.Gabe Black
2006-10-23Files in base shouldn't depend on things in sim. Changed "sim/host.hh" to <in...Gabe Black
2006-10-23Start making memory ops work with InitiateAcc and CompleteAcc, and some minor...Gabe Black
2006-10-23Change the default constructors to take ExtMachInsts rather than regular Mach...Gabe Black
2006-10-22Add mutex test to Benchmarks.py.Steve Reinhardt
2006-10-22Another missing case in a switch (like Nate's earlier fix).Steve Reinhardt
2006-10-22Have tracediff print warning if no traceflags are set.Steve Reinhardt
2006-10-21Small bug fixes for timing LL/SC. Better now butSteve Reinhardt
2006-10-21Add Quiesce trace flag to track CPU quiesce/wakeup events.Steve Reinhardt
2006-10-21Just give up if a store conditional misses completelySteve Reinhardt
2006-10-21Fix formatting that got screwed up when tabs were removed.Steve Reinhardt
2006-10-21Refactor coherence state table initialization.Steve Reinhardt
2006-10-21Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2006-10-21Get rid of unused handleTargets() function.Steve Reinhardt
2006-10-21Tweak a few things for better page fault debugging.Steve Reinhardt
2006-10-21Updated to work with new command line argument ordering.Steve Reinhardt
2006-10-21Merge zizzer.eecs.umich.edu:/bk/newmemNathan Binkert
2006-10-21Missing caseNathan Binkert
2006-10-20Add some default options, point it to the /dist version of the splash benchmarksRon Dreslinski
2006-10-20Merge zizzer:/bk/newmemRon Dreslinski
2006-10-20Clean up splash2 so it works in v2.0Ron Dreslinski
2006-10-20Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2006-10-20Construct a correct value of PYTHONHOME from the interpreterNathan Binkert
2006-10-20Give physical memory some latency to stress the systemRon Dreslinski
2006-10-20Add a config file in the example with the memtester and some parser options.Ron Dreslinski
2006-10-20Get rid of a variable put back by merge.Ron Dreslinski
2006-10-20Merge zizzer:/bk/newmemRon Dreslinski
2006-10-20Use fixPacket function everywhere.Ron Dreslinski
2006-10-20Use PacketPtr everywhereNathan Binkert
2006-10-19refactor code for the packet, get rid of packet_impl.hhNathan Binkert
2006-10-19initialize end, clean up loopNathan Binkert
2006-10-19Fix compile of m5.fastNathan Binkert
2006-10-19Delete unused file src/mem/cache.hhSteve Reinhardt
2006-10-19m5term: assume localhost if host name not provided.Steve Reinhardt
2006-10-19Fix corner case on assertion.Ron Dreslinski
2006-10-19Fix memtester to use functional access, fix cache to work functionally now th...Ron Dreslinski
2006-10-19Small changes:Ron Dreslinski