Age | Commit message (Collapse) | Author |
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Caveats:
- Even though memtest is ISA-independent, it will only
run for the Alpha builds, since there's no way to specify
ISA-independent reference files and I didn't want to commit
3 copies since I'm not sure we want to run it for all the
different ISAs anyway.
- Reference outputs were generated on my laptop,
so performance numbers will be low compared to zizzer.
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directory where tracediff is.
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definition as well as the declaration.
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in debugging mode (especially valuable for tracediff).
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into zed.eecs.umich.edu:/z/hsul/work/sparc/x86.m5
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into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem
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src/SConscript:
strip doesn't take a src and dest in solaris
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into zeep.pool:/z/saidi/work/m5.newmem
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src/arch/sparc/floatregfile.cc:
Fix serialization for fpreg
src/arch/sparc/intregfile.cc:
fix serialization for intreg
src/arch/sparc/miscregfile.cc:
fix serialization from miscreg
src/arch/sparc/pagetable.cc:
fix serialization for page table
src/arch/sparc/regfile.cc:
need to serialize nnpc
src/arch/sparc/tlb.cc:
write serialization code for tlb
src/cpu/base.cc:
provide a way to find the thread number a context is
serialize the instruction counter
src/cpu/base.hh:
provide a way to find the thread number a context is
and given a thread number find a context pointer
src/cpu/cpuevent.hh:
provide method to get thread context from a cpu event for serialization
src/dev/sparc/t1000.cc:
src/dev/sparc/t1000.hh:
nothing to serialize in t1000
src/sim/serialize.cc:
src/sim/serialize.hh:
Make findObj() work (it hasn't since we did the python conversion stuff)
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-m works as you think it should
Ctrl-C actually ends the simulation now
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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src/arch/sparc/isa/base.isa:
Added passesFpCondition function to help with fbfcc and fbpfcc instructions.
src/arch/sparc/isa/decoder.isa:
Added fbfcc and fbpfcc instructions, and cleaned up branch code slightly.
src/arch/sparc/isa/formats/branch.isa:
Minor cleanup.
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way to do this.
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of the pointer, not the memory.
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setSingleStep
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unimplemented floating point ops.
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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right with respect to quite NaNs, but hopefully we don't need to worry about the distinction.
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into zeep.pool:/z/saidi/work/m5.newmem
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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into zeep.pool:/z/saidi/work/m5.newmem
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into pb15.local:/Users/ali/work/m5.newmem.head
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return correct traps for ua2005 fpops that aren't implemented in hw
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into zeep.pool:/z/saidi/work/m5.newmem
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make fp writes also chatty with the Sparc traceflag
src/arch/sparc/floatregfile.cc:
make fp writes also chatty with the Sparc traceflag
src/cpu/exetrace.cc:
fix comparing fp registers between legion and m5
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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the other param code so that other functions can use it
as well.
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SConstruct:
src/SConscript:
Add flags for Intel CC while i'm at it
src/base/compiler.hh:
the _Pragma stuff needst to be called this way unless someone happens to have a cleaner way
src/base/cprintf_formats.hh:
add std:: where appropriate
src/base/statistics.hh:
use this->map since icc was getting confused about std::map vs the locally defined map
src/cpu/static_inst.hh:
Add some more dummy returns where needed
src/mem/packet.hh:
add more dummy returns where needed
src/sim/host.hh:
use limits to come up with max tick
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into zower.eecs.umich.edu:/eecshome/m5/newmem
src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/system.cc:
Hand Merge
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possible now becauase Ctrl_Base_DepTag gets added into control register numbers.
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into zeep.pool:/z/saidi/work/m5.newmem
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into zeep.pool:/z/saidi/work/m5.newmem
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some fixes to fp instructions to use the single precision registers
if this is an fp op emit fp check code
add fpregs to m5legion struct
src/arch/sparc/floatregfile.cc:
Make Sparc traceflag even more chatty
src/arch/sparc/isa/base.isa:
add code to check if the fpu is enabled
src/arch/sparc/isa/decoder.isa:
some fixes to fp instructions to use the single precision registers
fix smul again
fix subc/subcc/subccc condition code setting
src/arch/sparc/isa/formats/basic.isa:
src/arch/sparc/isa/formats/mem/util.isa:
if this is an fp op emit fp check code
src/cpu/exetrace.cc:
check fp regs as well as int regs
src/cpu/m5legion_interface.h:
add fpregs to m5legion struct
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