Age | Commit message (Collapse) | Author |
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"generic" devices are dependent on some of those files. That will either need to change, or most likely those devices will have to be considered architecture dependent.
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rename : src/dev/tsunami.cc => src/dev/alpha/tsunami.cc
rename : src/dev/tsunami.hh => src/dev/alpha/tsunami.hh
rename : src/dev/tsunami_cchip.cc => src/dev/alpha/tsunami_cchip.cc
rename : src/dev/tsunami_cchip.hh => src/dev/alpha/tsunami_cchip.hh
rename : src/dev/tsunami_io.cc => src/dev/alpha/tsunami_io.cc
rename : src/dev/tsunami_io.hh => src/dev/alpha/tsunami_io.hh
rename : src/dev/tsunami_pchip.cc => src/dev/alpha/tsunami_pchip.cc
rename : src/dev/tsunami_pchip.hh => src/dev/alpha/tsunami_pchip.hh
rename : src/dev/tsunamireg.h => src/dev/alpha/tsunamireg.h
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but isn't tested. Other architectures will not.
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from TheISA:: rather than AlphaISA::
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Alpha and SPARC and put SConscripts in them.
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rename : src/base/kgdb.h => src/arch/alpha/kgdb.h
rename : src/dev/alpha_access.h => src/dev/alpha/access.h
rename : src/dev/alpha_console.cc => src/dev/alpha/console.cc
rename : src/dev/alpha_console.hh => src/dev/alpha/console.hh
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because apparently you need an xc for that and not a tc. Cleaned up the TrapInstruction fault in light of this.
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can access it.
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PowerOnReset fault to kick start the CPU.
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don't know what it actually represents.
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could be improved and syscalls could be called from the trap's invoke method.
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src/arch/sparc/faults.cc:
Moved some code here from miscregfile.cc
src/arch/sparc/miscregfile.cc:
Moved code from here to faults.cc, and merged (read|set)MiscRegWithEffect and it's FS version from ua2005.cc
src/arch/sparc/miscregfile.hh:
readFSRegWithEffect is no longer a seperate function, and is instead done in the main readRegWith Effect.
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system.cc
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are in PAL mode, however.
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records when interrupts are requested, and returns an interrupt to execute if the
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
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should be able to boot into Linux with caches on after this change.
src/mem/bus.cc:
src/mem/bus.hh:
Bus now will be setup with a default responder, unless the user overrides it. This default responder should return BadAddress if no matching port is found.
src/python/m5/objects/Bus.py:
Bus now has a default responder for FS mode if the user doesn't override it. It returns BadAddress if no matching port is found.
src/python/m5/objects/Tsunami.py:
Add bad address device. Also record when the user has specified their own default responder.
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src/mem/cache/base_cache.cc:
Have caches return a new functional port whenever asked for them. I'm pretty sure this is desired behavior. Ron can correct me if it's not.
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src/cpu/simple_thread.cc:
Fix up port handling to share code.
src/cpu/thread_state.cc:
Separate code off into a function.
src/cpu/thread_state.hh:
Make a separate function that will get the CPU's memory's functional port.
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src/cpu/simple_thread.cc:
This function should have been deleted from an earlier push.
src/cpu/simple_thread.hh:
Delete this function; it's now in thread_state.hh/.cc.
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src/arch/alpha/utility.hh:
For now makeExtMI will be specific to the ISA.
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into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
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arbitrary CPU with or without caches.
configs/common/Simulation.py:
enable going from checkpoint into arbitrary CPU with or without caches.
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into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
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file functions to not take faults
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this will have only the o3 cpu have a cache, rather than timing (warmup) + o3 have cache.
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doens't get confused.
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corresponding to an IPR is readable or writable.
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code all over the place.
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the miscreg index of a specific IPR.
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configs/common/Simulation.py:
Remove mem parameter.
configs/example/se.py:
Remove debug output that got included in my other push.
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
configs/example/fs.py:
configs/example/se.py:
src/mem/tport.hh:
Hand merge.
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