Age | Commit message (Collapse) | Author |
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running SCons, make it into a sticky option that can be
overridden at build time, and set it up before the interpreter
is started. Also, fix the code that turns sticky options into
config/*.hh so that it works with types other than bool.
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
src/mem/tport.cc:
Merge PacketPtr changes
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extra : convert_revision : 0329c5803a3df67af3dda89bd9d4753fd1a286d1
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Fix fixPacket assert function.
Stop timing port from forwarding the request if a response was found in its queue on a read.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/python/m5/objects/MemTest.py:
Add parameter to configure what percentage of mem accesses are functional
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
Use fix Packet function
src/mem/packet.cc:
Fix an assert that was checking the wrong thing
src/mem/tport.cc:
Properly detect if we need to do the access to the functional device
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and call it packet_access.hh and fix the #includes so
things compile right.
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util/term/term.c:
Reindent.
util/term/term.c:
Assume localhost if only port number is given on command line.
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I need to move over to using the fixPacket function so I don't have to make the same changes everywhere.
Still a functional access bug someplace I need to track down in timing mode.
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
Fix corner case on assertion
tests/configs/memtest.py:
Updated memtester with uncacheable addresses and functional accesses
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that we could test it.
src/cpu/memtest/memtest.cc:
Fix memtest to do functional accesses
src/mem/cache/cache_impl.hh:
Fix cache to handle functional accesses properly based on memtester changes
Still need to fix functional accesses in timing mode now that the memtester can test it.
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extra : convert_revision : a6dbca4dc23763ca13560fbf5d41a23ddf021113
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?? doesn't compile in warn statements
Should have been false, where I had a true.
src/cpu/o3/lsq_impl.hh:
Apparently you can't have ?? in a warn statement (Something about trigraphs)
src/mem/cache/cache_impl.hh:
Forgot to signal atomic mode in snoopProbe
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extra : convert_revision : c75cb76e193e852284564993440c8ea39e6de426
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Now to try L2 caches in FS.
src/mem/cache/base_cache.hh:
Fix uni-coherence for atomic accesses in coherence protocol access to port
src/mem/cache/cache_impl.hh:
Properly handle uni-coherence
src/mem/cache/coherence/simple_coherence.hh:
Properly forward invalidates (not done for MSI+ protocols (assumed top level for now)
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
Properly forward invalidates in atomic/timing uni-coherence
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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src/mem/cache/cache_impl.hh:
Get the read data from the highest level of cache on a functional access
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Mark as satisfied for functional snoops.
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into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
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that tracing gets turned on as the very first thing
in the selected cycle (tick).
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configs/example/fs.py:
Add MOESI protocol to caches (uni coherence not quite working w/FS yet).
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to convert to System ptr first to access System method.
src/python/m5/SimObject.py:
how did i not commit this already? the other way doesn't seem to work.
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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Factor out some asserts that were on both
sides of an if/else.
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Reindent due to resulting changes in nesting.
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but not on zizzer... g++ 4 thing maybe?)
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configs/example/fs.py:
Add flag for MP server systems.
src/python/m5/objects/AlphaConsole.py:
src/python/m5/objects/IntrControl.py:
Change CPU from 'any' to 'cpu[0]' to work better with MP sytems.
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-timing-dual.py:
Don't need to set console & intrcontrol cpu
params anymore (default is fixed now).
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things and will test
src/mem/page_table.cc:
src/mem/page_table.hh:
add code to serialize/unserialize page table
src/sim/process.cc:
src/sim/process.hh:
add code to serialize/unserialize process
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Still a bug in atomic uni-coherence in FS.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
Make CPU models handle coherence requests
src/mem/cache/base_cache.cc:
Properly signal coherence CSHRs
src/mem/cache/coherence/uni_coherence.cc:
Only deallocate once
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after sending out a request.
Still need to rework upgrades into this system, but works for now.
src/mem/cache/base_cache.cc:
Re order code to be more readable
src/mem/cache/base_cache.hh:
Be sure to delete the copy on a bus block
src/mem/cache/cache_impl.hh:
Be sure to remove the copy on a writeback success
src/mem/cache/miss/mshr_queue.cc:
Demorgans to make it easier to understand
src/mem/tport.cc:
Delete writebacks
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writebacks delete the packet.
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sendTiming.
Still need to fix upgrades to use this path
src/mem/cache/base_cache.cc:
Copy the pkt to the MSHR before issuing the sendTiming where it may be changed/consumed
src/mem/cache/cache_impl.hh:
Use copy of packet, because sendTiming may have changed the pkt
Also, delete the copy when the time comes
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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Clean up a little.
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem_bus
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but I believe it should fix what she's running into (which was definitely a bug).
src/cpu/o3/fetch_impl.hh:
Move assertion to area where it should really always be true. Sometimes you might recvRetry and not necessarily be blocked (if there was a squash).
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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Fix CSHR's for flow control.
Fix for Bus Bridges reusing packets (clean flags up)
Now both timing/atomic caches with MOESI in UP fail at same point.
src/dev/io_device.hh:
DMA's should send WriteInvalidates
src/mem/bridge.cc:
Reusing packet, clean flags in the packet set by bus.
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
Fix CSHR's for flow control.
src/mem/packet.hh:
Make a writeInvalidateResp, since the DMA expects responses to it's writes
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