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2013-09-06ruby: network: correct naming of routersNilay Vaish
The routers are created before the network class. This results in the routers becoming children of the first link they are connected to and they get generic names like int_node and node_b. This patch creates the network object first and passes it to the topology creation function. Now the routers are children of the network object and names are much more sensible.
2013-09-06ruby: profiler: removes function resourceUsage()Nilay Vaish
2013-09-06ruby: remove undefined message size typeNilay Vaish
This message size type does not work well with one of the statistical variables. It also seems unnecessary.
2013-09-06ruby: network: removes reset functionalityNilay Vaish
2013-09-06ruby: network: shorten variable namesNilay Vaish
2013-09-06stats: adds a Formula operator for divisionNilay Vaish
2013-09-06ruby: converts sparse memory stats to gem5 styleNilay Vaish
2013-09-05sim: Fix clang warning for unused variableAndreas Hansson
This patch ensures the NULL ISA can build without causing issues with an unused variable.
2013-09-04util: Add ini string as tooltip info in dot outputAndreas Hansson
This patch adds the config ini string as a tooltip that can be displayed in most browsers rendering the resulting svg. Certain characters are modified for HTML output. Tested on chrome and firefox.
2013-09-04util: Add colours to the dot outputAndreas Hansson
This patch is adding a splash of colour to the dot output to make it easier to distinguish objects of different types. As a bonus, the pastel-colour palette also makes the output look like a something from the 21st century.
2013-09-04util: Add class name to dot graph and output to svgAndreas Hansson
This patch adds the class name to the label, creates some more space by increasing the rank separation, and additionally outputs the graph as an editable SVG in addition to the PDF.
2013-09-04tests: Move ISA-independent tests to the NULL ISAAndreas Hansson
This patch simply takes a first step to use the NULL ISA build for tests that do not make use of a CPU. Most of the Ruby tests could go the same way, but to avoid duplicating a lot of compilation targets that will have to wait until Ruby is built as a library and linked in independently. --HG-- rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini => tests/quick/se/50.memtest/ref/null/none/memtest/config.ini rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr => tests/quick/se/50.memtest/ref/null/none/memtest/simerr rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout => tests/quick/se/50.memtest/ref/null/none/memtest/simout rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt => tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/simerr => tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simerr rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/simout => tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt => tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/simerr => tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simerr rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/simout => tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt => tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt
2013-09-04arch: Resurrect the NOISA build target and rename it NULLAndreas Hansson
This patch makes it possible to once again build gem5 without any ISA. The main purpose is to enable work around the interconnect and memory system without having to build any CPU models or device models. The regress script is updated to include the NULL ISA target. Currently no regressions make use of it, but all the testers could (and perhaps should) transition to it. --HG-- rename : build_opts/NOISA => build_opts/NULL rename : src/arch/noisa/SConsopts => src/arch/null/SConsopts rename : src/arch/noisa/cpu_dummy.hh => src/arch/null/cpu_dummy.hh rename : src/cpu/intr_control.cc => src/cpu/intr_control_noisa.cc
2013-09-04cpu: Move the branch predictor out of the BaseCPUAndreas Hansson
The branch predictor is guarded by having either the in-order or out-of-order CPU as one of the available CPU models and therefore should not be used in the BaseCPU. This patch moves the parameter to the relevant CPU classes.
2013-09-04arch: Header clean up for NOISA resurrectionAndreas Hansson
This patch is a first step to getting NOISA working again. A number of redundant includes make life more difficult than it has to be and this patch simply removes them. There are also some redundant forward declarations removed.
2013-09-04alpha: Move system virtProxy to Alpha onlyAndreas Hansson
This patch moves the system virtual port proxy to the Alpha system only to make the resurrection of the NOISA slightly less painful. Alpha is the only ISA that is actually using it.
2013-09-04scons: Enable build on OSXAndreas Hansson
This patch changes the SConscript to build gem5 with libc++ on OSX as the conventional libstdc++ does not have the C++11 constructs that the current code base makes use of (e.g. std::forward). Since this was the last use of the transitional TR1, the unordered map and set header can now be simplified as well.
2013-08-26ARM: Fix configuration files for bare-metal binaries.Ali Saidi
2013-08-24stats: update eio statsSteve Reinhardt
2013-08-21util/regress: set --no-lto on regressionsSteve Reinhardt
See comment for motivation.
2013-08-20stats: update ruby.stats, config.ini files for x86 fs testNilay Vaish
2013-08-20ruby: add option for number of transitions per cycleNilay Vaish
The number of transitions per cycle that a controller can carry out is a proxy for the number of ports that a controller has. This value is currently 32 which is way too high. The patch introduces an option for the number of ports and uses this option in the protocol files to set the number of transitions. The default value is being set to 4. None of the se regressions change. Ruby stats for the fs regression change and are being updated.
2013-08-20cpu: Fix timing CPU isDrained comment formattingAndreas Hansson
This patch fixes up the comment formatting for isDrained in the timing CPU.
2013-08-20base: Fix VectorPrint initialisationAndreas Hansson
This patch changes how the initialisation of the VectorPrint struct is done so that gcc 4.4 is happy again.
2013-08-19stats: Cumulative stats updateAndreas Hansson
This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19cpu: Accurately count idle cycles for simple cpuLena Olson
Added a couple missing updates to the notIdleFraction stat. Without these, it sometimes gives a (not) idle fraction that is greater than 1 or less than 0.
2013-08-19config: Command line support for multi-channel memoryAndreas Hansson
This patch adds support for specifying multi-channel memory configurations on the command line, e.g. 'se/fs.py --mem-type=ddr3_1600_x64 --mem-channels=4'. To enable this, it enhances the functionality of MemConfig and moves the existing makeMultiChannel class method from SimpleDRAM to the support scripts. The se/fs.py example scripts are updated to make use of the new feature.
2013-08-19mem: Change AbstractMemory defaults to match the common caseAndreas Hansson
This patch changes the default parameter value of conf_table_reported to match the common case. It also simplifies the regression and config scripts to reflect this change.
2013-08-19cpu: Fix TrafficGen trace playbackSascha Bischoff
This patch addresses an issue with trace playback in the TrafficGen where the trace was reset but the header was not read from the trace when a captured trace was played back for a second time. This resulted in parsing errors as the expected message was not found in the trace file. The header check is moved to an init funtion which is called by the constructor and when the trace is reset. This ensures that the trace header is read each time when the trace is replayed. This patch also addresses a small formatting issue in a panic.
2013-08-19mem: Use STL deque in favour of list for DRAM queuesAndreas Hansson
This patch changes the data structure used for the DRAM read, write and response queues from an STL list to deque. This optimisation is based on the observation that the size is small (and fixed), and that the structures are frequently iterated over in a linear fashion.
2013-08-19mem: Perform write merging in the DRAM write queueAndreas Hansson
This patch implements basic write merging in the DRAM to avoid redundant bursts. When a new access is added to the queue it is compared against the existing entries, and if it is either intersecting or immediately succeeding/preceeding an existing item it is merged. There is currently no attempt made at avoiding iterating over the existing items in determining whether merging is possible or not.
2013-08-19mem: Replacing bytesPerCacheLine with DRAM burstLength in SimpleDRAMAmin Farmahini
This patch gets rid of bytesPerCacheLine parameter and makes the DRAM configuration separate from cache line size. Instead of bytesPerCacheLine, we define a parameter for the DRAM called burst_length. The burst_length parameter shows the length of a DRAM device burst in bits. Also, lines_per_rowbuffer is replaced with device_rowbuffer_size to improve code portablity. This patch adds a burst length in beats for each memory type, an interface width for each memory type, and the memory controller model is extended to reason about "system" packets vs "dram" packets and assemble the responses properly. It means that system packets larger than a full burst are split into multiple dram packets.
2013-08-19cpu: Fix timing CPU drain checkAndreas Hansson
This patch modifies the SimpleTimingCPU drain check to also consider the fetch event. Previously, there was an assumption that there is never a fetch event scheduled if the CPU is not executing microcode. However, when a context is activated, a fetch even is scheduled, and microPC() is zero.
2013-08-19alpha: Check interrupts before quiesceAndreas Hansson
This patch adds a check to the quiesce operation to ensure that the CPU does not suspend itself when there are unmasked interrupts pending. Without this patch there are corner cases when the CPU gets an interrupt before the quiesce is executed and then never wakes up again.
2013-08-19stats: Fix issue when printing 2D vectorsSascha Bischoff
This patch addresses an issue with the text-based stats output which resulted in Vector2D stats being printed without subnames in the event that one of the dimensions was of length 1. This patch also fixes the total printing for the 2D vector. Previously totals were printed without explicitly stating that a total was being printed. This has been rectified in this patch.
2013-08-19power: Add voltage domains to the clock domainsAkash Bagdia
This patch adds the notion of voltage domains, and groups clock domains that operate under the same voltage (i.e. power supply) into domains. Each clock domain is required to be associated with a voltage domain, and the latter requires the voltage to be explicitly set. A voltage domain is an independently controllable voltage supply being provided to section of the design. Thus, if you wish to perform dynamic voltage scaling on a CPU, its clock domain should be associated with a separate voltage domain. The current implementation of the voltage domain does not take into consideration cases where there are derived voltage domains running at ratio of native voltage domains, as with the case where there can be on-chip buck/boost (charge pumps) voltage regulation logic. The regression and configuration scripts are updated with a generic voltage domain for the system, and one for the CPUs.
2013-08-19config: Move the memory instantiation outside FSConfigAndreas Hansson
This patch moves the instantiation of the memory controller outside FSConfig and instead relies on the mem_ranges to pass the information to the caller (e.g. fs.py or one of the regression scripts). The main motivation for this change is to expose the structural composition of the memory system and allow more tuning and configuration without adding a large number of options to the makeSystem functions. The patch updates the relevant example scripts to maintain the current functionality. As the order that ports are connected to the memory bus changes (in certain regresisons), some bus stats are shuffled around. For example, what used to be layer 0 is now layer 1. Going forward, options will be added to support the addition of multi-channel memory controllers.
2013-08-19mem: Warn instead of panic for tXAW violationAndreas Hansson
Until the performance bug is fixed, avoid killing simulations.
2013-08-19mem: Allow disabling of tXAW through a 0 activation limitAndreas Hansson
This patch fixes an issue where an activation limit of 0 was not allowed. With this patch, setting the limit to 0 simply disables the tXAW constraint.
2013-08-19mem: Add an internal packet queue in SimpleMemoryAndreas Hansson
This patch adds a packet queue in SimpleMemory to avoid using the packet queue in the port (and thus have no involvement in the flow control). The port queue was bound to 100 packets, and as the SimpleMemory is modelling both a controller and an actual RAM, it potentially has a large number of packets in flight. There is currently no limit on the number of packets in the memory controller, but this could easily be added in a follow-on patch. As a result of the added internal storage, the functional access and draining is updated. Some minor cleaning up and renaming has also been done. The memtest regression changes as a result of this patch and the stats will be updated.
2013-08-19cpu: Fix a bug in the O3 CPU introduced by the cache line patchAndreas Hansson
This patch fixes a bug in the O3 fetch stage that was introduced when the cache line size was moved to the system. By mistake, the initialisation and resetting of the fetch stage was merged and put in the constructor. The resetting is now re-added where it should be.
2013-08-14arm: use -march when compiling m5op_arm.SAnthony Gutierrez
Using arm-linux-gnueabi-gcc 4.7.3-1ubuntu1 on Ubuntu 13.04 to compiled the m5 binary yields the error: m5op_arm.S: Assembler messages: m5op_arm.S:85: Error: selected processor does not support ARM mode `bxj lr' For each of of the SIMPLE_OPs. Apparently, this compiler doesn't like the interworking of these code types for the default arch. Adding -march=armv7-a makes it compile. Another alternative that I found to work is replacing the bxj lr instruction with mov pc, lr, but I don't know how that affects the KVM stuff and if bxj is needed.
2013-08-07ruby: slicc: remove double trigger, continueProcessingNilay Vaish
These constructs are not in use and are not being maintained by any one. In addition, it is not known if doubleTrigger works correctly with Ruby now.
2013-08-07ruby: slicc: move some code to AbstractControllerNilay Vaish
Some of the code in StateMachine.py file is added to all the controllers and is independent of the controller definition. This code is being moved to the AbstractController class which is the parent class of all controllers.
2013-08-07x86: add tlb checkpointingNilay Vaish
This patch adds checkpointing support to x86 tlb. It upgrades the cpt_upgrader.py script so that previously created checkpoints can be updated. It moves the checkpoint version to 6.
2013-07-19cpu: Remove unused getBranchPred() method from BaseCPUAndreas Sandberg
Remove unused virtual getBranchPred() method from BaseCPU as it is not implemented by any of the CPU models. It used to always return NULL.
2013-07-18Configs: Fix up maxtick and maxtimeJoel Hestness
This patch contains three fixes to max tick options handling in Options.py and Simulation.py: 1) Since the global simulator frequency isn't bound until m5.instantiate() is called, the maxtick resolution needs to happen after this call, since changes to the global frequency will cause m5.simulate() to misinterpret the maxtick value. Shuffling this also requires tweaking the checkpoint directory handling to signal the checkpoint restore tick back to run(). Fixing this completely and correctly will require storing the simulation frequency into checkpoints, which is beyond the scope of this patch. 2) The maxtick option in Options.py was defaulted to MaxTicks, so the old code would always skip over the maxtime part of the conditionals at the beginning of run(). Change the maxtick default to None, and set the maxtick local variable in run() appropriately. 3) To clarify whether max ticks settings are relative or absolute, split the maxtick option into separate options, for relative and absolute. Ensure that these two options and the maxtime option are handled appropriately to set the maxtick variable in Simulation.py.
2013-07-18config: Update script to set cache line size on systemAndreas Hansson
This patch changes the config scripts such that they do not set the cache line size per cache instance, but rather for the system as a whole.
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
This patch removes the notion of a peer block size and instead sets the cache line size on the system level. Previously the size was set per cache, and communicated through the interconnect. There were plenty checks to ensure that everyone had the same size specified, and these checks are now removed. Another benefit that is not yet harnessed is that the cache line size is now known at construction time, rather than after the port binding. Hence, the block size can be locally stored and does not have to be queried every time it is used. A follow-on patch updates the configuration scripts accordingly.
2013-07-18mem: Add cache class destructor to avoid memory leaksXiangyu Dong
Make valgrind a little bit happier