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2015-08-27ruby: handle llsc accesses through CacheEntry, not CacheMemoryNilay Vaish
The sequencer takes care of llsc accesses by calling upon functions from the CacheMemory. This is unnecessary once the required CacheEntry object is available. Thus some of the calls to findTagInSet() are avoided.
2015-08-26cpu: quiesce pseudoinsts: Always do full quiesceEmilio Castillo
The O3CPU blocks the Fetch when it sees a quiesce instruction (IsQuiesce flag). When the inst. is executed, a quiesce event is created to reactivate the context and unblock the Fetch. If the quiesceNs or quiesceCycles are called with a value of 0, the QuiesceEvent will not be created and the Fetch stage will remain blocked. Committed by Joel Hestness <jthestness@gmail.com>
2015-08-24mem: Revert requirement on packet addr/size always validAndreas Hansson
This patch reverts part of (842f56345a42), as apparently there are use-cases outside the main repository relying on the late setting of the physical address.
2015-08-21mem: Reflect that packet address and size are always validAndreas Hansson
This patch simplifies the packet, and removes the possibility of creating a packet without a valid address and/or size. Under no circumstances are these fields set at a later point, and thus they really have to be provided at construction time. The patch also fixes a case there the MinorCPU creates a packet without a valid address and size, only to later delete it.
2015-08-21arm, mem: Remove unused CLEAR_LL request flagAndreas Hansson
Cleaning up dead code. The CLREX stores zero directly to MISCREG_LOCKFLAG and so the request flag is no longer needed. The corresponding functionality in the cache tags is also removed.
2015-08-21mem: Remove unused cache squash functionalityAndreas Hansson
Tidying up.
2015-08-21mem: Add explicit Cache subclass and make BaseCache abstractAndreas Hansson
Open up for other subclasses to BaseCache and transition to using the explicit Cache subclass. --HG-- rename : src/mem/cache/BaseCache.py => src/mem/cache/Cache.py
2015-08-21ruby: Move Rubys cache class from Cache.py to RubyCache.pyAndreas Hansson
This patch serves to avoid name clashes with the classic cache. For some reason having two 'SimObject' files with the same name creates problems. --HG-- rename : src/mem/ruby/structures/Cache.py => src/mem/ruby/structures/RubyCache.py
2015-08-21mem: Move cache_impl.hh to cache.ccAndreas Hansson
There is no longer any need to keep the implementation in a header.
2015-08-21cpu: Move invldPid constant from Request to BaseCPUAndreas Hansson
A more natural home for this constant.
2015-08-19ruby: reverts to changeset: bf82f1f7b040Nilay Vaish
2015-08-14ruby: add accessor functions to SLICC def of MachineIDNilay Vaish
2015-08-14ruby: simple network: refactor codeNilay Vaish
Drops an unused variable and marks three variables as const.
2015-08-14ruby: profiler: provide the number of vnets through ruby systemNilay Vaish
The aim is to ultimately do away with the static function Network::getNumberOfVirtualNetworks().
2015-08-14ruby: directory memory: drop unused variable.Nilay Vaish
2015-08-14ruby: slicc: remove a stray line in StateMachine.pyNilay Vaish
2015-08-14ruby: garnet: flexible: refactor flitNilay Vaish
2015-08-14ruby: DataBlock: adds a commentNilay Vaish
2015-08-14ruby: remove random seedNilay Vaish
We no longer use the C library based random number generator: random(). Instead we use the C++ library provided rng. So setting the random seed for the RubySystem class has no effect. Hence the variable and the corresponding option are being dropped.
2015-08-14ruby: SubBlock: refactor codeNilay Vaish
2015-08-14ruby: cache recorder: move check on block size to RubySystem.Nilay Vaish
2015-08-14ruby: abstract controller: mark some variables as constNilay Vaish
2015-08-14ruby: simple network: store Switch* in PerfectSwitch and ThrottleNilay Vaish
2015-08-14ruby: remove unused functionalRead() function.Nilay Vaish
2015-08-14ruby: perfect switch: refactor codeNilay Vaish
Refactored the code in operateVnet(), moved partly to a new function operateMessageBuffer().
2015-08-14ruby: cache memory: drop {try,test}CacheAccess functionsNilay Vaish
2015-08-14ruby: call setMRU from L1 controllers, not from sequencerNilay Vaish
Currently the sequencer calls the function setMRU that updates the replacement policy structures with the first level caches. While functionally this is correct, the problem is that this requires calling findTagInSet() which is an expensive function. This patch removes the calls to setMRU from the sequencer. All controllers should now update the replacement policy on their own. The set and the way index for a given cache entry can be found within the AbstractCacheEntry structure. Use these indicies to update the replacement policy structures.
2015-08-14ruby: adds set and way indices to AbstractCacheEntryNilay Vaish
2015-08-14ruby: eliminate type uint64 and int64Nilay Vaish
These types are being replaced with uint64_t and int64_t.
2015-08-14ruby: slicc: use default argument valueNilay Vaish
Before this patch, while one could declare / define a function with default argument values, but the actual function call would require one to specify all the arguments. This patch changes the check for function arguments. Now a function call needs to specify arguments that are at least as much as those with default values and at most the total number of arguments taken as input by the function.
2015-08-14ruby: slicc: avoid duplicate code for function argument checkNilay Vaish
Both FuncCallExprAST and MethodCallExprAST had code for checking the arguments with which a function is being called. The patch does away with this duplication. Now the code for checking function call arguments resides in the Func class.
2015-08-14ruby: drop the [] notation for lookup function.Nilay Vaish
This is in preparation for adding a second arugment to the lookup function for the CacheMemory class. The change to *.sm files was made using the following sed command: sed -i 's/\[\([0-9A-Za-z._()]*\)\]/.lookup(\1)/' src/mem/protocol/*.sm
2015-08-14ruby: handle llsc accesses through CacheEntry, not CacheMemoryNilay Vaish
The sequencer takes care of llsc accesses by calling upon functions from the CacheMemory. This is unnecessary once the required CacheEntry object is available. Thus some of the calls to findTagInSet() are avoided.
2015-08-14stats: updates to ruby fs regression testNilay Vaish
Changes due to recent patches: fc1e41e88fd3, 882ce080c9f7, e8a6637afa4c, and e6e3b7097810 by Joel Hestness.
2015-08-14ruby: replace Address by AddrNilay Vaish
This patch eliminates the type Address defined by the ruby memory system. This memory system would now use the type Addr that is in use by the rest of the system.
2015-08-14ruby: rename variables Addr to addrNilay Vaish
Avoid clash between type Addr and variable name Addr.
2015-08-14stats: Bump for MessageBuffer, cache latency changesJoel Hestness
2015-08-14ruby: Protocol changes for SimObject MessageBuffersJoel Hestness
2015-08-14ruby: Expose MessageBuffers as SimObjectsJoel Hestness
Expose MessageBuffers from SLICC controllers as SimObjects that can be manipulated in Python. This patch has numerous benefits: 1) First and foremost, it exposes MessageBuffers as SimObjects that can be manipulated in Python code. This allows parameters to be set and checked in Python code to avoid obfuscating parameters within protocol files. Further, now as SimObjects, MessageBuffer parameters are printed to config output files as a way to track parameters across simulations (e.g. buffer sizes) 2) Cleans up special-case code for responseFromMemory buffers, and aligns their instantiation and use with mandatoryQueue buffers. These two special buffers are the only MessageBuffers that are exposed to components outside of SLICC controllers, and they're both slave ends of these buffers. They should be exposed outside of SLICC in the same way, and this patch does it. 3) Distinguishes buffer-specific parameters from buffer-to-network parameters. Specifically, buffer size, randomization, ordering, recycle latency, and ports are all specific to a MessageBuffer, while the virtual network ID and type are intrinsics of how the buffer is connected to network ports. The former are specified in the Python object, while the latter are specified in the controller *.sm files. Unlike buffer-specific parameters, which may need to change depending on the simulated system structure, buffer-to-network parameters can be specified statically for most or all different simulated systems.
2015-08-14ruby: Change PerfectCacheMemory::lookup to return pointerJoel Hestness
CacheMemory and DirectoryMemory lookup functions return pointers to entries stored in the memory. Bring PerfectCacheMemory in line with this convention, and clean up SLICC code generation that was in place solely to handle references like that which was returned by PerfectCacheMemory::lookup.
2015-08-14ruby: Remove the RubyCache/CacheMemory latencyJoel Hestness
The RubyCache (CacheMemory) latency parameter is only used for top-level caches instantiated for Ruby coherence protocols. However, the top-level cache hit latency is assessed by the Sequencer as accesses flow through to the cache hierarchy. Further, protocol state machines should be enforcing these cache hit latencies, but RubyCaches do not expose their latency to any existng state machines through the SLICC/C++ interface. Thus, the RubyCache latency parameter is superfluous for all caches. This is confusing for users. As a step toward pushing L0/L1 cache hit latency into the top-level cache controllers, move their latencies out of the RubyCache declarations and over to their Sequencers. Eventually, these Sequencer parameters should be exposed as parameters to the top-level cache controllers, which should assess the latency. NOTE: Assessing these latencies in the cache controllers will require modifying each to eliminate instantaneous Ruby hit callbacks in transitions that finish accesses, which is likely a large undertaking.
2015-08-11sim: clocked object: function for converting cycles to ticks.Nilay Vaish
2015-08-11ruby: drop some redundant includesNilay Vaish
2015-08-11ruby: slicc: allow mathematical operations on TicksNilay Vaish
2015-08-07sim: Flag EventQueue::getCurTick() as constAndreas Sandberg
2015-08-07stats: Update ARM stats to include programmable oscillatorsAndreas Sandberg
2015-08-07mem: Cleanup packet accessor methodsAndreas Sandberg
The Packet::get() and Packet::set() methods both have very strange semantics. Currently, they automatically convert between the guest system's endianness and the host system's endianness. This behavior is usually undesired and unexpected. This patch introduces three new method pairs to access data: * getLE() / setLE() - Get data stored as little endian. * getBE() / setBE() - Get data stored as big endian. * get(ByteOrder) / set(v, ByteOrder) - Configurable endianness For example, a little endian device that is receiving a write request will use teh getLE() method to get the data from the packet. The old interface will be deprecated once all existing devices have been ported to the new interface.
2015-08-07dev: Implement a simple display timing generatorAndreas Sandberg
Timing generator for a pixel-based display. The timing generator is intended for display processors driving a standard rasterized display. The simplest possible display processor needs to derive from this class and override the nextPixel() method to feed the display with pixel data. Pixels are ordered relative to the top left corner of the display. Scan lines appear in the following order: * Vertical Sync (starting at line 0) * Vertical back porch * Visible lines * Vertical front porch Pixel order within a scan line: * Horizontal Sync * Horizontal Back Porch * Visible pixels * Horizontal Front Porch All events in the timing generator are automatically suspended on a drain() request and restarted on drainResume(). This is conceptually equivalent to clock gating when the pixel clock while the system is draining. By gating the pixel clock, we prevent display controllers from disturbing a memory system that is about to drain.
2015-08-07arm: Add support for programmable oscillatorsAndreas Sandberg
Add support for oscillators that can be programmed using the RealView / Versatile Express configuration interface. These oscillators are typically used for things like the pixel clock in the display controller. The default configurations support the oscillators from a Versatile Express motherboard (V2M-P1) with a CoreTile Express A15x2.
2015-08-07dev: Add a simple DMA engine that can be used by devicesAndreas Sandberg
Add a simple DMA engine that sits behind a FIFO. This engine can be used by devices that need to read large amounts of data (e.g., display controllers). Most aspects of the controller, such as FIFO size, maximum number of in-flight accesses, and maximum request sizes can be configured. The DMA copies blocks of data into its FIFO. Transfers are initiated with a call to startFill() command that takes a start address and a size. Advanced users can create a derived class that overrides the onEndOfBlock() callback that is triggered when the last request to a block has been issued. At this point, the DMA engine is ready to start fetching a new block of data, potentially from a different address range. The DMA engine stops issuing new requests while it is draining. Care must be taken to ensure that devices that are fed by a DMA engine are suspended while the system is draining to avoid buffer underruns.