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AgeCommit message (Expand)Author
2019-03-21ext,tests: Make return code based on test resultsJason Lowe-Power
2019-03-21ext,test: Provide default terminal sizeJason Lowe-Power
2019-03-21cpu-kvm: Added informative error messageRyan Gambord
2019-03-20mem-cache: Added the STeMS prefetcherJavier Bueno
2019-03-19systemc: Hook up gem5_getPort to the gem5 getPort mechanism.Gabe Black
2019-03-19arch, cpu, dev, gpu, mem, sim, python: start using getPort.Gabe Black
2019-03-19python: Switch to the new getPort mechanism to connect ports.Gabe Black
2019-03-19mem: Move bind() and unbind() into the Port class.Gabe Black
2019-03-19sim: Add a getPort function to SimObject.Gabe Black
2019-03-19util: Build m5 with -no-pie flagRyan Gambord
2019-03-18python: Change || to && for MessageBuffers in connectPorts.Gabe Black
2019-03-18python: Improve how templated SimObject classes are handled.Gabe Black
2019-03-18scons: fix disable_partial logic for fast binaryHoa Nguyen
2019-03-18util: changed shebang on gem5img.py to python2.7Ryan Gambord
2019-03-18mem-cache: tautological comparison of byteOrderAndrea Mondelli
2019-03-18configs: Use absolute import pathsAndreas Sandberg
2019-03-15mem: Removed circular include refRyan Gambord
2019-03-15mem-cache: Added the Indirect Memory PrefetcherJavier Bueno
2019-03-15mem: Move the Port base class into sim.Gabe Black
2019-03-15dev: Make EtherInt inherit from Port.Gabe Black
2019-03-15mem: Track the MemObject owner in MasterPort and SlavePort.Gabe Black
2019-03-15python: Simplify connectPorts() around EtherObject/EtherDevice.Gabe Black
2019-03-15dev: Make the EtherDevice class inherit EtherObject.Gabe Black
2019-03-15dev: Turn EtherObject into an interface class.Gabe Black
2019-03-15mem-cache: Fix write hit latency calculation orderDaniel
2019-03-14python: Teach cxxMethod how to set return_value_policy.Gabe Black
2019-03-14python: Teach PyBindMethod how to set return_value_policy.Gabe Black
2019-03-14cpu: Refactor of Physical Register implementationAndrea Mondelli
2019-03-14python: Fix unknown params and proxy multiplicationDaniel R. Carvalho
2019-03-14dev-arm: cleanup of gicv3 CPU interface code and fixesJairo Balart
2019-03-14arch-arm,cpu: Add initial support for Arm SVEGiacomo Gabrielli
2019-03-12scons: Don't use isdir in AddLocalRPATH.Gabe Black
2019-03-12sim: Add size to array unserialization error messageDaniel R. Carvalho
2019-03-12dev-arm: cleanup of gicv3 codeJairo Balart
2019-03-12mem-cache: Removed default arg from get() in prefetch/base.hhRyan Gambord
2019-03-11arch-hsail: changed gen.py shebang from python(3) to python2.7Ryan Gambord
2019-03-11arch-arm: Fixing implicit fallthrough build errorsRyan Gambord
2019-03-11mem-cache: Revert "mem-cache: Remove Packet dependency in Tags"Daniel R. Carvalho
2019-03-10mem-cache: Added extra information to PrefetchInfoJavier Bueno
2019-03-07mem-cache: Add header delay to handleFill whenReadyDaniel R. Carvalho
2019-03-07mem-cache: Allow tag-only accesses on latency calculationDaniel R. Carvalho
2019-03-07mem-cache: Add lookup latency to access' whenReadyDaniel R. Carvalho
2019-03-07mem-cache: Fix recvTimingReq doWritebacks tickDaniel R. Carvalho
2019-03-07mem-cache: Use header delay on latency calculationDaniel R. Carvalho
2019-03-07mem-cache: Remove old todo about latency in hit functionDaniel R. Carvalho
2019-03-01util, tlm: Fix a memory error in the SCMasterPort class.Gabe Black
2019-03-01tlm: Add some includes to some tlm_utils header files.Gabe Black
2019-03-01python: Fix issue when Self proxy resolves to a another proxyAndreas Sandberg
2019-03-01mem-cache: alias to mem::getMasterPort in TLB classAndrea Mondelli
2019-03-01dev-arm: Set ICV_PMR_EL1-ICH_VMCR_EL2 mapping on readsGiacomo Travaglini
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