Age | Commit message (Collapse) | Author |
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--HG--
extra : convert_revision : 626255a91679d534030c91bcdb4fc1bed36ceb9b
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Stats pretty much line up with old code, except:
- bug in old code included L1 latency in L2 miss time, making it too high
- UniCoherence did cache-to-cache transfers even from non-owner caches,
so occasionally the icache would get a block from the dcache not the L2
- L2 can now receive ReadExReq from L1 since L1s have coherence
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extra : convert_revision : 5052c1a1767b5a662f30a88f16012165a73b791c
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now encoded in cmd field.
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extra : convert_revision : d67819b7e3ee4b9a5bf08541104de0a89485e90b
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into vm1.(none):/home/stever/bk/newmem-cache2
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extra : convert_revision : 1e94283da8007fce8e1a0f2849ce5d5a8dbbaffd
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src/arch/mips/isa/decoder.isa:
commment out deret instruction for now...
src/arch/mips/isa/formats/fp.isa:
edit fp format
src/arch/mips/isa/formats/mem.isa:
fix for basic store instructions
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extra : convert_revision : 30cb5a474e78ac9292b6ab37d433db947a177731
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into vm1.(none):/home/stever/bk/newmem-cache2
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extra : convert_revision : b1c954c187e3b3172a194396ba63808253121195
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--HG--
extra : convert_revision : 2c0be7a8c0a54ba5b1b2b69468f788d20abc8452
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extra : convert_revision : 4ff144342dca23af9a12a2169ca318a002654b42
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--HG--
extra : convert_revision : 9bc09d8ae6d50e6dfbb4ab21514612f9aa102a2e
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--HG--
extra : convert_revision : 703da6128832eb0d5cfed7724e5105f4b3fe4f90
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Change target overflow from assertion to warning.
src/mem/cache/cache_impl.hh:
Change target overflow from assertion to warning.
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extra : convert_revision : ceca990ed916bbf96dedd4836c40df522803f173
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src/mem/cache/tags/lru.cc:
Add some replacement DPRINTFs
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extra : convert_revision : 7993ec24d6af7e7774d04ce36f20e3f43f887fd9
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src/mem/cache/cache_impl.hh:
Handle grants with no packet.
src/mem/cache/miss/mshr.cc:
Fix MSHR snoop hit handling.
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extra : convert_revision : f365283afddaa07cb9e050b2981ad6a898c14451
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sure we don't re-request bus prematurely. Use callback to
avoid calling sendRetry() recursively within recvTiming.
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extra : convert_revision : a907a2781b4b00aa8eb1ea7147afc81d6b424140
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--HG--
extra : convert_revision : 0fbc28c32c1eeb3dd672df14c1d53bd516f81d0f
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into vm1.(none):/home/stever/bk/newmem-cache2
src/base/traceflags.py:
Hand merge.
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extra : convert_revision : 9e7539eeab4220ed7a7237457a8f336f79216924
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src/cpu/memtest/memtest.cc:
Need to set packet source field so that response from cache
doesn't run into assertion failure when copying source to dest.
src/mem/packet.hh:
Copy source field when copying packets.
Assert that source is valid before copying it to dest
when turning packets around.
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extra : convert_revision : 09e3cfda424aa89fe170e21e955b295746832bf8
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ControlBitfieldOPerand to ISA Parser. Now, while things do build, we have to fix broken functionality...
src/arch/isa_parser.py:
add back deleted writeback in Control Operand
--HG--
extra : convert_revision : dba11af220a1281fa53f79d87e4f8752bdfc56db
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--HG--
extra : convert_revision : 31e7243c8820cb9f6744c53c417460dee9adaf44
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into vm1.(none):/home/stever/bk/newmem-cache2
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extra : convert_revision : aa50af3094f5d459f75b514179b6e3ec5e0bf1df
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src/arch/mips/SConscript:
"mips import pt.1".
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extra : convert_revision : 2e393341938bebf32fb638a209262d074fad4cc1
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into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/newmem-o3-micro
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extra : convert_revision : 3fa3fa4544ff8c9d2135e1befe6c8f4757006a2a
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mcf has a reduced input size, and most of the other changes are for a change in how branch mispredicts work which makes things more accurate.
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extra : convert_revision : 33ad6a220945b344d2fc5c6abef8e67467e0c0ec
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into vm1.(none):/home/stever/bk/newmem-cache2
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extra : convert_revision : 1da75335907fee2d1745ec13e515819dfe2aad89
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Single-cpu timing mode seems to work now.
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extra : convert_revision : 720f6172df18a1c941e5bd0e8fdfbd686c13c7ad
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--HG--
extra : convert_revision : 28a6df1efe4298877dc2b20179caeb25dfdc4622
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--HG--
extra : convert_revision : d8d139180917f54006a5a79df4a0f206ddd39fed
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-micro
src/cpu/o3/fetch_impl.hh:
hand merge
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extra : convert_revision : 3f71f3ac2035eec8b6f7bceb6906edb4dd09c045
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
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extra : convert_revision : ba4d93f354749d02278b16e78b4ecd4b2311416b
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--HG--
extra : convert_revision : 3626c4d2d67ed190d846f6edae06c43444a14feb
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into vm1.(none):/home/stever/bk/newmem-cache2
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extra : convert_revision : 9002940097a166c8442ae1adf41b974227968920
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configs/example/memtest.py:
Add progress interval option.
src/base/traceflags.py:
Add MemTest flag.
src/cpu/memtest/memtest.cc:
Clean up tracing.
src/cpu/memtest/memtest.hh:
Get rid of unused code.
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extra : convert_revision : 92bd8241a6c90bfb6d908e5a5132cbdb500cbb87
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don't spend so much time calling malloc()
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extra : convert_revision : a946564eee46ed7d2aed41c32d488ca7f036c32f
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extra : convert_revision : 005464e875ede1e37dfe0e0482c29fd793ca52be
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extra : convert_revision : 9e57e582dd1ef2805d5adffcc0ccfd99596d9f54
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--HG--
extra : convert_revision : 1fd66ba519d211fec18641b6df94b7640c56080c
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extra : convert_revision : 17e67cf6ea17fe6f971ef608547983fbb94adec9
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an "ID", and also added support for symbols.
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extra : convert_revision : 60d1ef677a6a59a9d897086893843ec1ec368148
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extra : convert_revision : 7342cd4a1700a247f30d6f85fc6c2685341ba20e
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--HG--
extra : convert_revision : 2b10076a24cb36cb748e299011ae691f09c158cd
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--HG--
extra : convert_revision : 99053414cef40f13c5226871a72909b2622d8c26
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displacement.
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extra : convert_revision : 9202c11ee187458adcd85ba616b7f7f4bdd4eec1
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--HG--
extra : convert_revision : c4a76262d4396f5f5b96b1c9e751014c2abbd78a
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--HG--
extra : convert_revision : bea87214ba4b40d75a350b803154836ec6d0ae9e
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--HG--
extra : convert_revision : 9df17841d970a7995d8ed1d51ee66e2c5457e5e3
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--HG--
extra : convert_revision : f489fda15740bae0a73bfb012f3bab5790b5c2b5
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--HG--
extra : convert_revision : aabaaf099f070832bf42cedf2472170e0738ee1c
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
--HG--
extra : convert_revision : f2fac2b1a09e709021cd8382a9fbe805df2177ef
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--HG--
extra : convert_revision : 514032e21c8861f20fcbcae7204e132088cc7dbc
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