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2011-06-02scons: rename TraceFlags to DebugFlagsNathan Binkert
2011-06-02scons: rename some things from m5 to gem5Nathan Binkert
The default generated binary is now gem5.<type> instead of m5.<type>. The latter does still work but gem5.<type> will be generated first and then m5.<type> will be hard linked to it.
2011-06-02copyright: Add code for finding all copyright blocks and create a COPYING fileNathan Binkert
The end of the COPYING file was generated with: % python ./util/find_copyrights.py configs src system tests util Update -C command line option to spit out COPYING file
2011-06-02copyright: clean up copyright blocksNathan Binkert
2011-06-01SimObject: allow modules in subclass definitionsSteve Reinhardt
In particular, this avoids crashing when you do an import (like "import pdb") inside a SimObject subclass definition.
2011-05-31orion: bug fix in link power, and some reorgTushar Krishna
2011-05-31garnet: added network ptr to links to be used by orionTushar Krishna
2011-05-29Misc: Remove the URL from warnings, fatals, panics, etc.Gabe Black
2011-05-25Name: Replace M5 with gem5 in a few places it's printed on startup.Gabe Black
2011-05-24style: Make the style hook work in directories other than the root.Nathan Binkert
2011-05-23sim: style fixes in sim/process.hhSteve Reinhardt
2011-05-23syscall emul: fix Power Linux mmap constant, plus other cleanupSteve Reinhardt
We were getting a spurious warning in the regressions that turned out to be due to having the wrong value for TGT_MAP_ANONYMOUS for Power Linux, but in the process of tracking it down I ended up doing some cleanup of the mmap handling in general.
2011-05-23config: revamp x86 config to avoid appending to SimObjectVectorsSteve Reinhardt
A significant contributor to the need for adoptOrphanParams() is the practice of appending to SimObjectVectors which have already been assigned as children. This practice sidesteps the assignment operation for those appended SimObjects, which is where parent/child relationships are typically established. This patch reworks the config scripts that use append() on SimObjectVectors, which all happen to be in the x86 system configuration. At some point in the future, I hope to make SimObjectVectors immutable (by deriving from tuple rather than list), at which time this patch will be necessary for correct operation. For now, it just avoids some of the warning messages that get printed in adoptOrphanParams().
2011-05-23config: tweak ruby configs to clean up hierarchySteve Reinhardt
Re-enabling implicit parenting (see previous patch) causes current Ruby config scripts to create some strange hierarchies and generate several warnings. This patch makes three general changes to address these issues. 1. The order of object creation in the ruby config files makes the L1 caches children of the sequencer rather than the controller; these config ciles are rewritten to assign the L1 caches to the controller first. 2. The assignment of the sequencer list to system.ruby.cpu_ruby_ports causes the sequencers to be children of system.ruby, generating warnings because they are already parented to their respective controllers. Changing this attribute to _cpu_ruby_ports fixes this because the leading underscore means this is now treated as a plain Python attribute rather than a child assignment. As a result, the configuration hierarchy changes such that, e.g., system.ruby.cpu_ruby_ports0 becomes system.l1_cntrl0.sequencer. 3. In the topology classes, the routers become children of some random internal link node rather than direct children of the topology. The topology classes are rewritten to assign the routers to the topology object first.
2011-05-23config: reinstate implicit parenting on parameter assignmentSteve Reinhardt
Last summer's big rewrite of the initialization code (in particular cset 6efc3672733b) got rid of the implicit parenting that used to occur when an unparented SimObject was assigned as a parameter value to another SimObject. The idea was that the new adoptOrphanParams() step would catch these anyway so it was unnecessary. Unfortunately it turns out that adoptOrphanParams() has some inherent instability in that the parent that does the adoption depends on the config tree traversal order. Even making this order deterministic (e.g., by traversing children in alphabetical order) can introduce unwanted and unexpected hierarchy changes between similar configs (e.g., when adding a switch_cpu in place of a cpu), causing problems when trying to restore checkpoints across similar configs. The hierarchy created by implicit parenting is more stable and more controllable, so this patch turns that behavior back on. This patch also cleans up some long-standing holes regarding parenting of SimObjects that are created in class definitions (either in the body of the class, or as default parameters). To avoid breaking some existing config files, this necessitated changing the error on reparenting children to a warning. This change fixes another bug where attempting to print the prior error message would fail on reparenting SimObjectVectors because they lack a _parent attribute. Some further issues with SimObjectVectors were cleaned up by getting rid of the get_parent() call (which could cause errors with some SimObjectVectors where there was no single parent to return) with has_parent() (since all the uses of get_parent() were just boolean tests anyway). Finally, since the adoptOrphanParam() step turned out to be so problematic, we now issue a warning when it actually has to do an adoption. Future cleanup of config files will get rid of current warnings.
2011-05-23sim: add some DPRINTFs for debugging unserializationSteve Reinhardt
Also got rid of unused C++ unserializeAll() method (this is now handled in Python)
2011-05-23util/regress: make default action a more thorough regressionSteve Reinhardt
Changed the --variants option to --test-variants and added a new --compile-variants option for variants that are only compiled (not tested). The former still defaults to 'opt' and the latter defaults to 'debug,fast'. Also changed the behavior when no tests are specified from just compiling to running the 'quick' tests. As a result, a plain 'util/regress' invocation will now compile (but not test) the debug and fast builds, and compile and run the quick regressions on the opt build. This should be the default set of tests that are run before committing. Since the nightly regressions use this same script, this will also be the new nightly regression behavior. Test-only regressions can still be done by setting --compile=''. Compile-only regressions can be done by setting --test=''.
2011-05-23configs: missed spot progress-interval changeKorey Sewell
2011-05-23Stats: Update stats for minor O3 changes below.Ali Saidi
2011-05-23O3: Fix offset calculation into storeQueue buffer for store->load forwardingGeoffrey Blake
Calculation of offset to copy from storeQueue[idx].data structure for load to store forwarding fixed to be difference in bytes between store and load virtual addresses. Previous method would induce bug where a load would index into buffer at the wrong location.
2011-05-23O3: Fix issue w/wbOutstading being decremented multiple times on blocked cache.Geoffrey Blake
If a split load fails on a blocked cache wbOutstanding can be decremented twice if the first part of the split load succeeds and the second part fails. Condition the decrementing on not having completed the first part of the load.
2011-05-23O3: Fix issue with interrupts/faults occuring in the middle of a macro-opGeoffrey Blake
This patch fixes two problems with the O3 cpu model. The first is an issue with an instruction fetch causing a fault on the next address while the current macro-op is being issued. This happens when the micro-ops exceed the fetch bandwdith and then on the next cycle the fetch stage attempts to issue a request to the next line while it still has micro-ops to issue if the next line faults a fault is attached to a micro-op in the currently executing macro-op rather than a "nop" from the next instruction block. This leads to an instruction incorrectly faulting when on fetch when it had no reason to fault. A similar problem occurs with interrupts. When an interrupt occurs the fetch stage nominally stops issuing instructions immediately. This is incorrect in the case of a macro-op as the current location might not be interruptable.
2011-05-21garnet: use vnet_type from protocol to decide buffer depthsTushar Krishna
The virtual channels within "response" vnets are made buffers_per_data_vc deep (default=4), while virtual channels within other vnets are made buffers_per_ctrl_vc deep (default = 1). This is for accurate power estimates.
2011-05-21configs: remove -p from ruby_network_test.pyTushar Krishna
A recent patch broke the ruby network tester by adding -p inside Options.py which conflicts with the -p inside ruby_network_test.py. Have removed -p from ruby_network_test.py
2011-05-20configs: cleanup redundant/unused optionsKorey Sewell
maxinsts & max_inst redundant prog_intvl and profile seem redundant, but profile looks to be unused add -p option for progress intervals
2011-05-20slicc: added vnet_type to MI_exampleTushar Krishna
Forgot to add this to MI_example in my previous patch.
2011-05-18gcc: fix an uninitialized variable warning from G++ 4.5Nathan Binkert
2011-05-18slicc: added vnet_type field to identify response vnets from othersTushar Krishna
Identifying response vnets versus other vnets will allow garnet to determine which vnets will carry data packets, and which will carry ctrl packets, and use appropriate buffer sizes (since data packets are larger than ctrl packets). This in turn allows the orion power model to accurately estimate buffer power.
2011-05-18garnet: rename and rearrange config parameters.Tushar Krishna
Renamed (message) class to vnet for consistency with rest of ruby. Moved some parameters specific to fixed/flexible garnet networks into their corresponding py files.
2011-05-13ARM: Fix up stats for previous changes to condition codesAli Saidi
2011-05-13ARM: Generate condition code setting code based on which codes are set.Ali Saidi
This change further eliminates cases where condition codes were being read just so they could be written without change because the instruction in question was supposed to preserve them. This is done by creating the condition code code based on the input rather than just doing a simple substitution.
2011-05-13ARM: Construct the predicate test register for more instruction programatically.Ali Saidi
If one of the condition codes isn't being used in the execution we should only read it if the instruction might be dependent on it. With the preeceding changes there are several more cases where we should dynamically pick instead of assuming as we did before.
2011-05-13ARM: Further break up condition code into NZ, C, V bits.Ali Saidi
Break up the condition code bits into NZ, C, V registers. These are individually written and this removes some incorrect dependencies between instructions.
2011-05-13ARM: Remove the saturating (Q) condition code from the renamed register.Ali Saidi
Move the saturating bit (which is also saturating) from the renamed register that holds the flags to the CPSR miscreg and adds a allows setting it in a similar way to the FP saturating registers. This removes a dependency in instructions that don't write, but need to preserve the Q bit.
2011-05-13ARM: Break up condition codes into normal flags, saturation, and simd.Ali Saidi
This change splits out the condcodes from being one monolithic register into three blocks that are updated independently. This allows CPUs to not have to do RMW operations on the flags registers for instructions that don't write all flags.
2011-05-13Trace: Allow printing ASIDs and selectively tracing based on user/kernel code.Chander Sudanthi
Debug flags are ExecUser, ExecKernel, and ExecAsid. ExecUser and ExecKernel are set by default when Exec is specified. Use minus sign with ExecUser or ExecKernel to remove user or kernel tracing respectively.
2011-05-13ARM: Better RealView/Versatile EB platform support.Chander Sudanthi
Add registers and components to better support the VersatileEB board. Made the MIDR and SYS_ID register parameters to ArmSystem and RealviewCtrl respectively.
2011-05-13O3: Fix an issue with a load & branch instruction and mem dep squashingGeoffrey Blake
Instructions that load an address and are control instructions can execute down the wrong path if they were predicted correctly and then instructions following them are squashed. If an instruction is a memory and control op use the predicted address for the next PC instead of just advancing the PC. Without this change NPC is used for the next instruction, but predPC is used to verify that the branch was successful so the wrong path is silently executed.
2011-05-12stats: delete mysql supportNathan Binkert
we can add it back within python in some future changeset
2011-05-12stats: move code that loops over all stats into pythonNathan Binkert
2011-05-12stats: better expose statistics to python.Nathan Binkert
Build a python list and dict of all stats and expose flags properly. --HG-- rename : src/python/m5/stats.py => src/python/m5/stats/__init__.py
2011-05-09work around gcc 4.5 warningNathan Binkert
2011-05-07NetworkTest: added sim_cycles parameter to the network tester.Tushar Krishna
The network tester terminates after injecting for sim_cycles (default=1000), instead of having to explicitly pass --maxticks from the command line as before. If fixed_pkts is enabled, the tester only injects maxpackets number of packets, else it keeps injecting till sim_cycles. The tester also works with zero command line arguments now.
2011-05-07network: added Torus and Pt2Pt topologiesTushar Krishna
2011-05-07Trace: Remove the options trace-help and trace-flagsNilay Vaish
The options trace-help and trace-flags are no longer required. In there place, the options debug-help and debug-flags have been provided.
2011-05-06X86: Fix the Lldt instructions so they load the ldtr and not the tr.Gabe Black
2011-05-05ruby: use RubyMemory flag & remove setDebug() functionalityKorey Sewell
The RubyMemory flag wasnt used in the code, creating large gaps in trace output. Replace cprintfs w/dprintfs using RubyMemory in memory controller. DPRINTF also deprecate the usage of the setDebug() pure virtual function in the AbstractMemoryOrCache Class as well the m_debug/cprintf functions in MemoryControl.hh/cc
2011-05-04ARM: Update ARM_FS stats for mp changesAli Saidi
2011-05-04ARM: Configure bootloader parametersAli Saidi
2011-05-04ARM: Add support for loading the a bootloader and configuring parameters for itAli Saidi