gem5 - gem5

Age	Commit message (Expand)	Author
2010-08-20	ruby: Reincarnated the responding machine profiling	Brad Beckmann
2010-08-20	MOESI_CMP_token: Fixed dma persistent lockdown bugs	Brad Beckmann
2010-08-20	memtest: Memtester support for DMA	Brad Beckmann
2010-08-20	ruby: Added ruby_request_type ostream def to libruby.hh	Brad Beckmann
2010-08-20	slicc: Consolidated the protocol stats printing	Brad Beckmann
2010-08-20	config: Improve ruby simobject names	Brad Beckmann
2010-08-20	config: Added the topology description to m5 config.ini	Brad Beckmann
2010-08-20	ruby: added token broadcast config params to cmd options	Brad Beckmann
2010-08-20	config: reorganized how ruby specifies command-line options	Brad Beckmann
2010-08-20	ruby: Fixed printout when Sequencer detects a deadlock	Brad Beckmann
2010-08-20	MESI_CMP_directory: bug fix for old PUTX requests	Brad Beckmann
2010-08-20	config: moved python protocol config files	Brad Beckmann
2010-08-17	misc: add some AMD copyright notices	Steve Reinhardt
2010-08-17	x86: minor checkpointing bug fixes	Steve Reinhardt
2010-08-17	sim: revamp unserialization procedure	Steve Reinhardt
2010-08-17	sim: fold checkpoint restore code into instantiate()	Steve Reinhardt
2010-08-17	configs: clean up checkpoint code in Simulation.py	Steve Reinhardt
2010-08-17	test: Update stats for python object iteration.	Steve Reinhardt
2010-08-17	sim: clean up child handling	Steve Reinhardt
2010-08-17	sim: move iterating over SimObjects into Python.	Steve Reinhardt
2010-08-17	sim: fail on implicit creation of orphans via ports	Steve Reinhardt
2010-08-17	sim: make Python Root object a singleton	Steve Reinhardt
2010-08-17	tests: update reference config.ini files for previous cset	Steve Reinhardt
2010-08-17	bus: clean up default responder code.	Steve Reinhardt
2010-08-14	Inorder: Fix compilation of m5.fast.	Gabe Black
2010-08-13	Merge with head.	Gabe Black
2010-08-13	CPU: Add readBytes and writeBytes functions to the exec contexts.	Gabe Black
2010-08-13	InOrder: Clean up some DPRINTFs that print data sent to/from the cache.	Gabe Black
2010-08-13	CPU: Tidy up endianness handling for mmapped "IPR"s.	Gabe Black
2010-08-12	util/m5/m5.c: ensure readfile() buffer pages are in page table	Joel Hestness
2010-08-12	TimingSimpleCPU: fix NO_ACCESS memory op handling	Joel Hestness
2010-08-08	None, not none	Nathan Binkert
2010-07-27	.hgignore: added src/doxygen	Steve Reinhardt
2010-07-27	ARM: Add regression tests	Ali Saidi
2010-07-22	Power: The condition register should be set or cleared upon a system call	Timothy M. Jones
2010-07-22	LSQ Unit: After deleting part of a split request, set it to NULL so that it	Timothy M. Jones
2010-07-22	Port: Only indicate that a SimpleTimingPort is drained if its send event is	Timothy M. Jones
2010-07-22	O3CPU: Fix a bug where stores in the cpu where never marked as split.	Timothy M. Jones
2010-07-22	Syscall: Don't close the simulator's standard file descriptors.	Timothy M. Jones
2010-07-22	O3CPU: O3's tick event gets squashed when it is switched out. When repeatedly	Timothy M. Jones
2010-07-22	Power: Provide a utility function to copy registers from one thread context	Timothy M. Jones
2010-07-21	stats: unify the two stats distribution type better	Nathan Binkert
2010-07-21	stats: cleanup a few small problems in stats	Nathan Binkert
2010-07-21	python: add a sorted dictionary class	Nathan Binkert
2010-07-21	python: Add mechanism to override code compiled into the exectuable	Nathan Binkert
2010-07-21	Fix x86 XCHG macro-op to use locked micro-ops for all memory accesses	Tushar Krishna
2010-07-17	SimObject: transparently forward Python attribute refs to C++.	Steve Reinhardt
2010-07-15	ARM: Make an SRS instruction with a bad mode cause an undefined instruction f...	Gabe Black
2010-07-13	ARM: Adjust the FP_Base_DepTag to be larger than the largest int reg index.	Gabe Black
2010-07-08	cache: fix bug in SC upgrade handling	Steve Reinhardt