gem5 - gem5

Age	Commit message (Expand)	Author
2007-08-13	SPARC: Move tlb state into the tlb.	Gabe Black
2007-08-13	SPARC: Make the spill and fill handlers use the correct ASI, and let No_Fault...	Gabe Black
2007-08-13	Move the "translate" member functions back into the base o3 class.	Gabe Black
2007-08-13	python: make the DictImporter's unload() work in any context.	Nathan Binkert
2007-08-12	Style: fix IGNORE_STYLE so it isn't required on the command line.	Ali Saidi
2007-08-12	Regression: fix configuration for SPARC_FS	Ali Saidi
2007-08-12	Regression: Update stats for cache changes.	Ali Saidi
2007-08-12	MemorySystem: Fix the use of ?: to produce correct results.	Ali Saidi
2007-08-12	merge	Nathan Binkert
2007-08-12	style: If IGNORE_STYLE=True is set on the scons command line, ignore style.	Nathan Binkert
2007-08-08	Added fastmem option.	Vincentius Robby
2007-08-08	alpha: Quick fix for things related to TLB MRU cache.	Vincentius Robby
2007-08-10	Regression: Add an I/O Cache to the full system regressions that have a cache.	Ali Saidi
2007-08-10	DMA: Add IOCache and fix bus bridge to optionally only send requests one	Ali Saidi
2007-08-10	Bus: Only call end() on an stl object once in a loop	Ali Saidi
2007-08-08	Port, StaticInst: Revert unnecessary changes.	Vincentius Robby
2007-08-08	alpha: Make the TLB cache to actually work.	Vincentius Robby
2007-08-07	Alpha: Fix an off by one error with the tlb caching mechanism.	Gabe Black
2007-08-07	Merge with head.	Gabe Black
2007-08-07	Statetrace: Make statetrace do string instructions all at once like m5 does.	Gabe Black
2007-08-07	X86: Added some missing parenthesis in the condition code calculation function.	Gabe Black
2007-08-07	X86: Implemented and hooked in SCAS (scan string)	Gabe Black
2007-08-07	X86: Add a format to handle string instructions which can use the repe and re...	Gabe Black
2007-08-07	X86: Overhaul of ruflags to get it to work correctly.	Gabe Black
2007-08-07	X86: Make a microcode branch microop.	Gabe Black
2007-08-04	Merge with head.	Gabe Black
2007-08-04	X86: Implement microops and instructions that manipulate the flags register.	Gabe Black
2007-08-04	X86: Make 64 bit unaligned accesses work as well as the other sizes.	Gabe Black
2007-08-04	X86: Make the open flags correct.	Gabe Black
2007-08-04	X86: Make fixed register operands ignore register index extensions from the R...	Gabe Black
2007-08-04	X86: Implement the cmpxchg instruction.	Gabe Black
2007-08-04	X86: Start implementing segmentation support.	Gabe Black
2007-08-04	X86: Create a base enum value for indexing into a region of the miscregs.	Gabe Black
2007-08-04	X86: Add the arch_prctl system call and fix up some microcoding.	Gabe Black
2007-08-04	switching: turn on profiling after a switch if there's an event	Nathan Binkert
2007-08-04	switching: Remove the drain and resume code from the switching code.	Nathan Binkert
2007-08-04	python: use the enum values in the memory mode changing code	Nathan Binkert
2007-08-04	swig: %include all of the enums to get all of the definitions.	Nathan Binkert
2007-08-04	merge	Nathan Binkert
2007-08-04	python: provide access to stats	Nathan Binkert
2007-08-04	main: return an an exit code of 1 when we exit due to a python exception.	Nathan Binkert
2007-08-04	SimpleCPU: Add some DPRINTFs	Nathan Binkert
2007-08-04	port: Implement cache for port interfaces and ranges	Vincentius Robby
2007-08-04	alpha: Implement a cache for recently used page table entries	Vincentius Robby
2007-08-04	StaticInst: Fix decode cache initialization. Cache functionality was negated.	Vincentius Robby
2007-08-03	Add cscope files to .hgignore.	Steve Reinhardt
2007-08-03	tests: new ref outputs for new cache model	Steve Reinhardt
2007-08-03	tests: replace all dest ref files on upgrade (if possible).	Steve Reinhardt
2007-08-03	tests: config.out no longer exists, eliminate ref copy.	Steve Reinhardt
2007-08-03	merge from head	Steve Reinhardt