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--HG--
extra : convert_revision : f8427ed6caa815500cbb0ce648f2495a2d039082
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so for consistency I changed it.
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami.hh:
change PCIConfigAll to PciConfigAll
--HG--
extra : convert_revision : d2fa3f59b906c870fd9d46cfa94728c7587e3652
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(very painful) bus reset from occuring
base/loader/elf_object.cc:
Fixed to allow proper loading of local symbols
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extra : convert_revision : 5c9a1f4d7b5748a1c8cabdfd67763c21f988f8fd
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and a physical memory address for DMA
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
Changed registers to array and added mapping function to translate between
PCI bus space and physical address space
--HG--
extra : convert_revision : e9dc4de4e7effe8e8e2365298843d6f767b5a289
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into zizzer.eecs.umich.edu:/z/alschult/DiskModel/m5
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extra : convert_revision : 9c69ae2810bef16e0e6625b1977588204e7b19e3
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--HG--
extra : convert_revision : 0a795251653c999eb099d192392302a7939f24d0
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for other mp testbenches
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extra : convert_revision : a962c67f63d059d25077a1bd4278f0d04737da04
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are present
dev/tsunami_cchip.cc:
Only need to interrupt processors that are there
Move RTC interrupt code into a function
dev/tsunami_cchip.hh:
Make a RTC interrupt function, move variables out of public scope
dev/tsunami_io.cc:
Make a call to the RTC interrupt routine instead
--HG--
extra : convert_revision : 88113664d0e54a7dddc00ec11ff9b9d088232b31
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dev/tsunami_cchip.cc:
Add support for IPI, making changes to read/write to MISC register
Particularly the IPREQ, IPINTR, and ITINTR subfields
dev/tsunami_cchip.hh:
Make an array to keep track of the number of outstanding IPI's,
Extend RTC to interrupt all processors, not just cpu0
dev/tsunami_io.cc:
Extend RTC to interrupt all present proccessors, not just cpu0
--HG--
extra : convert_revision : 0715cbf0abb06002c0fb0b05ef369304cdf75001
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base/cprintf_formats.hh:
Add additional format modifiers
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extra : convert_revision : f9ec0a664eeb96db7dacacd6b7636e3cb47555e7
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physical addressing. This has the uncacheable bit as bit 40 as opposed
to bit 39. Additionally, we now support (at least superficially) a 44-bit
physical address. To deal with superpage access in this scheme, any super
page access with either bit 39 or 40 set is sign extended.
--HG--
extra : convert_revision : 05ddbcb9a6a92481109a63b261743881953620ab
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arch/alpha/alpha_memory.cc:
SCCS merged
--HG--
extra : convert_revision : 0348e29c833684fd593a6c02913319f45f24e76e
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physical addresses.
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extra : convert_revision : efb4a5229d88cb3c024e0b24f5916048bd42d589
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physical address
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extra : convert_revision : c51b5d3e09b4d5384cb113ab2ed569ef9a1f2ab4
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--HG--
extra : convert_revision : 901ef4782d0c9f0d842deba7acdba7896da7e41c
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dev/tsunami_cchip.cc:
fixed another problem with the interrupt code, should all work now
--HG--
extra : convert_revision : 1d9fe6081b6391e3e09f1c4a9380a30240fac6dc
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--HG--
extra : convert_revision : 3fb611e6e0305fe9854cdf7813492b75750cd7a9
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dev/tsunami_cchip.cc:
Change interrupt level to 20 for devices
--HG--
extra : convert_revision : deee68d5434643dc751de08e5a804c14d1a86efd
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in adaptec_ctrl.hh
cpu/base_cpu.cc:
changed index to 64bits
cpu/base_cpu.hh:
changed index to 64 bits
--HG--
extra : convert_revision : e70d5f09f6066b90fca82cae22bb7d7eb705d65e
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dev/tsunami_cchip.cc:
SCCS merged
--HG--
extra : convert_revision : a4b2b0b92038217608a733a6c8f27edb018e910d
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interrupt to use a different subnumber since both devices could
interrupt at the same time and we don't want to loose one.
dev/tsunami_cchip.cc:
rewrote interrupt code to handle interrupt mask clearing correctly
dev/tsunami_cchip.hh:
changed (post/clear)DRIR to use a interrupt number rather than a vecotr
dev/tsunami_io.cc:
updated for new post/clearDRIR calls
--HG--
extra : convert_revision : 5b39f5e15a66d5eb6e689e6ece62f99b5fa735ab
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dev/tsunami_cchip.cc:
Changed to point to IPL 20 rather than 21
--HG--
extra : convert_revision : ee70f4bae4e06b92a0e02ea71ed65d4e260e7967
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--HG--
extra : convert_revision : 3ef3d2c7eb67c45a7e005c1c072f3098142ea210
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--HG--
extra : convert_revision : f274a32072c1c0ff2de99724f4597a46341df6ae
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--HG--
extra : convert_revision : 2bfc338decdceaaf57f4a391b93882a8e0715a56
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cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
Add 2 new parameters to control the percentage of unaligned copy sources and destinations.
--HG--
extra : convert_revision : 2646ee2f195e9f3e76bc257b8716163ef63a9f40
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arch/alpha/vtophys.cc:
base/remote_gdb.cc:
Fix to remote debugger while in PAL code
dev/pcidev.cc:
Remove extra debug printf
--HG--
extra : convert_revision : e64988846ad05cd3ddf47034d72d99dae3501591
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into zizzer.eecs.umich.edu:/z/alschult/linux
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extra : convert_revision : 2ea2bbd41f7e0c257b374d9cd0e37abaf6a7c170
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arch/alpha/vtophys.cc:
fix up vtophys to deal with translations if there
is no ptbr, and to deal with PAL addresses
add ptomem which is just a wrapper for dma_addr
arch/alpha/vtophys.hh:
add ptomem which is a wrapper for dma_addr with the
same usage as vtomem
--HG--
extra : convert_revision : 1ae22073d400e87b708a4a7ef501124227fc6c39
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dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/tsunami_uart.cc:
SCCS merged
--HG--
extra : convert_revision : da3d1998d6dd39e0d3f8754074c513cdd8a4193c
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--HG--
extra : convert_revision : 468f3c739707d167af43562695b604fd7dead661
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--HG--
extra : convert_revision : 964126edcf72faf572a9272599264ba2f5cd7aa1
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arch/alpha/alpha_linux_process.cc:
Fixes for Linux emulation:
- stat struct alignment
- osf_{get,set}sysinfo return values
- additional syscall numbers
- initialize $r0 to 0
sim/syscall_emul.cc:
brk(0) just returns brk value (don't update it!)
--HG--
extra : convert_revision : 78e22458321c81e81540d101c9e65e2e4b0ad117
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Changed base_linux.ini file to use physical addresses
dev/alpha_console.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
Fix masking of read/write address to get read/write offset
dev/tsunami_uart.cc:
Fix masking of read/write address to get read/write offset
Also added add_child call that was missed
dev/tsunami_uart.hh:
Changed size to 0x8
--HG--
extra : convert_revision : 1468ca43167bfb28b28c4510401a1ebad683e102
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--HG--
extra : convert_revision : 643dc6bbd4f60437cee7518e8ae011cee32e2263
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cpu/memtest/memtest.cc:
Add traceBlockAddr to trace outputs.
--HG--
extra : convert_revision : e4ebaf9647fb393448367f4f4af3bae566f51c24
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some sundry problems with new interface
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/baddev.cc:
dev/baddev.hh:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunami_uart.cc:
dev/tsunami_uart.hh:
Fixed to use new FunctionalMemory interface
--HG--
extra : convert_revision : bee98e6285d92f28fafacf919ab06eaf333a9b56
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arch/alpha/alpha_memory.cc:
dev/alpha_console.cc:
dev/alpha_console.hh:
Merge
--HG--
extra : convert_revision : 3233648f204338ab3f102ff117754dce955dcc37
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--HG--
extra : convert_revision : 0c018b88d6ca80b1690ec99d795014848e375e44
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Aligned copies now fully work in LRU (just need to write the IIC doCopy call). At the moment they are slow since a stalled copy stalls the entire cache.
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
Add aligned copy tests, percent of copies is specified by percent_copies
--HG--
extra : convert_revision : eaf1900fcb8832db98249e94e3472ebfb049eb48
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--HG--
extra : convert_revision : c11fde5e5f0e344d2f4c89c57a4d41ca179a31e5
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dev/tsunami.hh:
Added generic platform base class
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extra : convert_revision : ff74956937f9fca5bdfa5e3779add776e4a91f8b
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into zizzer.eecs.umich.edu:/y/saidi/work/m5
--HG--
extra : convert_revision : 35c2de18adad0957538453b2a083e59de535aa88
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dev/pcidev.cc:
Linux 2.6 writes the latency timer, so it was added to the list of
allowable writes
dev/tsunami_uart.cc:
dev/tsunami_uart.hh:
A couple of changes so that the new linux autoconf serial driver thinks
that the serial port exists and configures it
--HG--
extra : convert_revision : 6c026ef754e31de56c9b837ceb8f6be48c8d8d9c
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- Make the MemoryController use address ranges (via Range) instead
of an address and a mask
base/remote_gdb.cc:
reflect name change
dev/alpha_access.h:
better include
dev/alpha_console.cc:
- FunctionalMemory no longer takes care of mapping my address into
the proper address space. It must be done locally.
- the memory controller no longer uses a mask, but a size, and the
size is determined by the device, not the .ini file
- fix up address calculations to reflect the removal of a mask
- PhysicalMemory::getSize() -> PhysicalMemory::size()
dev/alpha_console.hh:
- FunctionalMemory no longer takes care of mapping my address into
the proper address space. It must be done locally.
- the memory controller no longer uses a mask, but a size, and the
size is determined by the device, not the .ini file
- fix up address calculations to reflect the removal of a mask
- get rid of MmapDevice and inherit from FunctionalMemory
--HG--
extra : convert_revision : e3a65c9debf6f899632d62c70781cbdc2826616b
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into zizzer.eecs.umich.edu:/.automount/ziff/z/binkertn/research/m5/memory
--HG--
extra : convert_revision : 9f385ee5b6958373a9a1bc600eb3e5e8b7987f38
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--HG--
extra : convert_revision : 81b365ac9ca8b33cae99107e5b1900f7c46f0866
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base/range.hh:
Add a constructor that takes the beginning and end as arguments
size returns T not a bool
quick make_range() function that is a shortcut for making a range
kinda like make_pair()
quick formatting fix
--HG--
extra : convert_revision : 94b1d462710e6fb55e72e1da2ad8c46993af1ef7
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(bk auto merge messed these up...)
--HG--
extra : convert_revision : 5ebda321ab5ac4b85a1d846affa0035ded853b9d
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--HG--
extra : convert_revision : 87b2c4a4a83eec7d696d9d84d14dbdc7532849f9
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