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It runs out that if a MemObject turns around and does a send in its
receive callback, and there are other sends already scheduled, then
it could observe a state where it's not at the head of the list but
the bus's sendEvent is not scheduled (because we're still in the
middle of processing the prior sendEvent).
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I was asserting that the only reason you would defer targets is if
a write came in while you had an outstanding read miss, but there's
another case where you could get a read access after you've snooped
an invalidation and buffered it because it applies to a prior
outstanding miss.
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"behind" the pci config magic ports.
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classes.
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variant of iret.
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Instead of computing the segment descriptor address, this now checks if a
selector value/descriptor are legal for a particular purpose.
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than one register is accessed at a time.
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calculating it.
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memory microcode.
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