gem5 - gem5

Age	Commit message (Collapse)	Author
2011-07-02	ExecContext: Get rid of the now unused read/write templated functions.	Gabe Black

2011-07-02	ISA: Use readBytes/writeBytes for all instruction level memory operations.	Gabe Black

2011-07-02	Stats: Update stats for the x86 store fault fix.	Gabe Black

2011-07-02	X86: Fix store microops so they don't drop faults in timing mode.	Gabe Black
	If a fault was returned by the CPU when a store initiated it's write, the store instruction would ignore the fault. This change fixes that.
2011-07-01	Ruby: Commit files missing from previous commit	Nilay Vaish
	The previous commit on functional access support in Ruby did not have some of the files required. This patch adds those files to the repository.
2011-06-30	Regression: Updates regression outputs for Ruby memtest	Brad Beckmann
	This patch updates the regression outputs for Ruby memtest. This was required because of the changes carried out by the addition of functional access support to Ruby.
2011-06-30	config: removed unnecessary slashes	Brad Beckmann
	This patch removes unnecessary slashes from a couple of python scripts.
2011-06-30	Ruby: Add support for functional accesses	Brad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
	This patch rpovides functional access support in Ruby. Currently only the M5Port of RubyPort supports functional accesses. The support for functional through the PioPort will be added as a separate patch.
2011-06-28	arch: print next upc correctly	Nilay Vaish
	The patch corrects the print statement which prints the current and the next pc. Instead of the next upc, the next pc was being printed.
2011-06-24	Ruby: remove unused functions in CacheMemory: get/setMemoryValue	Joel Hestness

2011-06-22	mips: fix nmsub and nmadd definitions	Deyaun Guo
	the -/+ signs were flipped for nmsub_s, nmsub_d, and nmadd_d
2011-06-21	X86: Eliminate an unused argument for building store microops.	Gabe Black

2011-06-20	inorder: sparc: add 02.insttest regression	Korey Sewell

2011-06-20	inorder: sparc: add hello world regression	Korey Sewell
	- add InOrderCPU compile option to SPARC - add hello regression for SPARC
2011-06-20	merge regression updates	Korey Sewell

2011-06-20	alpha:o3:simple: update simout/err files	Korey Sewell
	A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-20	inorder: alpha-hello regression update	Korey Sewell

2011-06-20	inorder: merge gabes compile fix	Korey Sewell

2011-06-20	InOder: Fix a compile error.	Gabe Black

2011-06-19	inorder: gem5.opt compile	Korey Sewell
	variable name typo.
2011-06-19	inorder: update eon regr w/eon info	Korey Sewell
	previous commit copied over O3 stats, this one puts the inorder ones in the right place
2011-06-19	inorder: add 10.linux-boot regression	Korey Sewell

2011-06-19	inorder: add eon regression	Korey Sewell

2011-06-19	inorder: update SE regressions	Korey Sewell

2011-06-19	inorder: clear reg. dep entry after removing from list	Korey Sewell
	this will safeguard future code from trying to remove from the list twice. That code wouldnt break but would waste time.
2011-06-19	inorder: se: squash after syscalls	Korey Sewell

2011-06-19	inorder: cleanup dprintfs in cache unit	Korey Sewell

2011-06-19	inorder: SE mode TLB faults	Korey Sewell
	handle them like we do in FS mode, by blocking the TLB until the fault is handled by the fault->invoke()
2011-06-19	inorder:tracing: fix fault tracing bug	Korey Sewell

2011-06-19	inorder: se compile fixes	Korey Sewell

2011-06-19	inorder: add necessary debug flag header files	Korey Sewell

2011-06-19	mips: mark unaligned access flag as true	Korey Sewell

2011-06-19	inorder: clear fetchbuffer on traps	Korey Sewell
	implement clearfetchbufferfunction extend predecoder to use multiple threads and clear those on trap
2011-06-19	inorder: use separate float-reg bits function in dyninst	Korey Sewell
	this will make sure we get the correct view of a FP register
2011-06-19	inorder: use trapPending flag to manage traps	Korey Sewell

2011-06-19	inorder/dtb: make sure DTB translate correct address	Korey Sewell
	The DTB expects the correct PC in the ThreadContext but how if the memory accesses are speculative? Shouldn't we send along the requestor's PC to the translate functions?
2011-06-19	inorder: handle serializing instructions	Korey Sewell
	including IPR accesses and store-conditionals. These class of instructions will not execute correctly in a superscalar machine
2011-06-19	alpha: fix warn_once for prefetches	Korey Sewell

2011-06-19	alpha: naming for dtb faults	Korey Sewell
	Just "dfault" gets confusing while debugging. Why not differentiate whether it's an access violation or page fault
2011-06-19	inorder: dont handle multiple faults on same cycle	Korey Sewell
	if a faulting instruction reaches an execution unit, then ignore it and pass it through the pipeline. Once we recognize the fault in the graduation unit, dont allow a second fault to creep in on the same cycle.
2011-06-19	inorder: register ports for FS mode	Korey Sewell
	handle "snoop" port registration as well as functional port setup for FS mode
2011-06-19	inorder: check for interrupts each tick	Korey Sewell
	use a dummy instruction to facilitate the squash after the interrupts trap
2011-06-19	inorder: explicit fault check	Korey Sewell
	Before graduating an instruction, explicitly check fault by making the fault check it's own separate command that can be put on an instruction schedule.
2011-06-19	inorder: squash and trap behind a tlb fault	Korey Sewell

2011-06-19	inorder: stall stores on store conditionals & compare/swaps	Korey Sewell

2011-06-19	alpha: make hwrei a control inst	Korey Sewell
	this always changes the PC and is basically an impromptu branch instruction. why not speculate on this instead of always be forced to mispredict/squash after the hwrei gets resolved? The InOrder model needs this marked as "isControl" so it knows to update the PC after the ALU executes it. If this isnt marked as control, then it's going to force the model to check the PC of every instruction at commit (what O3 does?), and that would be a wasteful check for a very high percentage of instructions.
2011-06-19	inorder: make InOrder CPU FS compilable/visible	Korey Sewell
	make syscall a SE mode only functionality copy over basic FS functions (hwrei) to make FS compile
2011-06-19	inorder: remove memdep tracking for default pipeline	Korey Sewell
	speculative load/store pipelines can reenable this
2011-06-19	inorder: fetchBuffer tracking	Korey Sewell
	calculate blocks in use for the fetch buffer to figure out how many total blocks are pending
2011-06-19	inorder: redefine DynInst FP result type	Korey Sewell
	Sharing the FP value w/the integer values was giving inconsistent results esp. when their is a 32-bit integer register matched w/a 64-bit float value