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2014-11-06tests: A test program for the new mwait implementation.Marc Orr
This is a simple test program for the new mwait implemenation. It is uses m5threads to create to threads of execution in syscall emulation mode that interact using the mwait instruction. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-11-06cpu: Minor Draining BugAndrew Lukefahr
Fixes a bug where Minor drains in the midst of committing a conditional store. While committing a conditional store, lastCommitWasEndOfMacroop is true (from the previous instruction) as we still haven't finished the conditional store. If a drain occurs before the cache response, Minor would check just lastCommitWasEndOfMacroop, which was true, and set drainState=DrainHaltFetch, which increases the streamSeqNum. This caused the conditional store to be squashed when the memory responded and it completed. However, to the memory the store succeeded, while to the instruction sequence it never occurred. In the case of an LLSC, the instruction sequence will replay the squashed STREX, which will fail as the cache is no longer in LLSC. Then the instruction sequence will loop back to a LDREX, which receives the updated (incorrect) value. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-11-06stats: updates due to changes to rubyNilay Vaish
2014-11-06ruby: provide a backing storeNilay Vaish
Ruby's functional accesses are not guaranteed to succeed as of now. While this is not a problem for the protocols that are currently in the mainline repo, it seems that coherence protocols for gpus rely on a backing store to supply the correct data. The aim of this patch is to make this backing store configurable i.e. it comes into play only when a particular option: --access-backing-store is invoked. The backing store has been there since M5 and GEMS were integrated. The only difference is that earlier the system used to maintain the backing store and ruby's copy was write-only. Sometime last year, we moved to data being supplied supplied by ruby in SE mode simulations. And now we have patches on the reviewboard, which remove ruby's copy of memory altogether and rely completely on the system's memory to supply data. This patch adds back a SimpleMemory member to RubySystem. This member is used only if the option: access-backing-store is set to true. By default, the memory would not be accessed.
2014-11-06ruby: interface with classic memory controllerNilay Vaish
This patch is the final in the series. The whole series and this patch in particular were written with the aim of interfacing ruby's directory controller with the memory controller in the classic memory system. This is being done since ruby's memory controller has not being kept up to date with the changes going on in DRAMs. Classic's memory controller is more up to date and supports multiple different types of DRAM. This also brings classic and ruby ever more close. The patch also changes ruby's memory controller to expose the same interface.
2014-11-06ruby: remove the function functionalReadBuffers()Nilay Vaish
This function was added when I had incorrectly arrived at the conclusion that such a function can improve the chances of a functional read succeeding. As was later realized, this is not possible in the current setup. While the code using this function was dropped long back, this function was not. Hence the patch.
2014-11-06ruby: coherence protocols: remove data block from dirctory entryNilay Vaish
This patch removes the data block present in the directory entry structure of each protocol in gem5's mainline. Firstly, this is required for moving towards common set of memory controllers for classic and ruby memory systems. Secondly, the data block was being misused in several places. It was being used for having free access to the physical memory instead of calling on the memory controller. From now on, the directory controller will not have a direct visibility into the physical memory. The Memory Vector object now resides in the Memory Controller class. This also means that some significant changes are being made to the functional accesses in ruby.
2014-11-06ruby: slicc: allow adding a bool to an int, like C++.Nilay Vaish
2014-11-06ruby: remove sparse memory.Nilay Vaish
In my opinion, it creates needless complications in rest of the code. Also, this structure hinders the move towards common set of code for physical memory controllers.
2014-11-06ruby: single physical memory in fs modeNilay Vaish
Both ruby and the system used to maintain memory copies. With the changes carried for programmed io accesses, only one single memory is required for fs simulations. This patch sets the copy of memory that used to reside with the system to null, so that no space is allocated, but address checks can still be carried out. All the memory accesses now source and sink values to the memory maintained by ruby.
2014-11-06ruby: dma sequencer: remove RubyPort as parent classNilay Vaish
As of now DMASequencer inherits from the RubyPort class. But the code in RubyPort class is heavily tailored for the CPU Sequencer. There are parts of the code that are not required at all for the DMA sequencer. Moreover, the next patch uses the dma sequencer for carrying out memory accesses for all the io devices. Hence, it is better to have a leaner dma sequencer.
2014-11-03tests: Update stats no match.Ali Saidi
Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-10-30arm, tests: Forgot the system.terminal files for the new regressions.Ali Saidi
2014-10-29arm, tests: Add 64-bit ARM regression testsAli Saidi
2014-10-29automated mergeAli Saidi
2014-10-29tests: Update regressions for the new kernels and various preceeding fixes.Ali Saidi
2014-10-29arm, tests: Update config files to more recent kernels and create 64-bit ↵Ali Saidi
regressions. This changes the default ARM system to a Versatile Express-like system that supports 2GB of memory and PCI devices and updates the default kernels/file-systems for AArch64 ARM systems (64-bit) to support up to 32GB of memory and PCI devices. Some platforms that are no longer supported have been pruned from the configuration files. In addition a set of 64-bit ARM regressions have been added to the regression system.
2014-10-29cpu: Add writeback modeling for drain functionalityMitch Hayenga
It is possible for the O3 CPU to consider itself drained and later have a squashed instruction perform a writeback. This patch re-adds tracking of in-flight instructions to prevent falsely signaling a drained event.
2014-10-29cpu: Add drain check functionality to IEWMitch Hayenga
IEW did not check the instQueue and memDepUnit to ensure they were drained. This caused issues when drainSanityCheck() did check those structures after asserting IEW was drained.
2014-10-29arm, mem: Fix drain bug and provide drain prints for more components.Ali Saidi
2014-10-29arm: Fix multi-system AArch64 boot w/caches.Ali Saidi
Automatically extract cpu release address from DTB file. Check SCTLR_EL1 to verify all caches are enabled.
2014-10-29arm: fix bare-metal memory setup.Ali Saidi
The bare-metal configuration option still configured memory with the old scheme that no-longer works. This change unifies the code so there aren't any differences.
2014-10-29arm: Mark some miscregs (timer counter) registers at unverifiable.Ali Saidi
The checker can't verify timer registers, so it should just grab the version from the executing CPU, otherwise it could get a larger value and diverge execution.
2014-10-29cpu: Add support to checker for CACHE_BLOCK_ZERO commands.Ali Saidi
The checker didn't know how to properly validate these new commands.
2014-10-29cpu: Fix barrier push to store buffer when full bug in MinorAndrew Bardsley
This patch fixes a bug where a completing load or store which is also a barrier can push a barrier into the store buffer without first checking that there is a free slot. The bug was not fatal but would print a warning that the store buffer was full when inserting.
2014-10-21mem: don't inhibit WriteInv's or defer snoops on their MSHRsCurtis Dunham
WriteInvalidate semantics depend on the unconditional writeback or they won't complete. Also, there's no point in deferring snoops on their MSHRs, as they don't get new data at the end of their life cycle the way other transactions do. Add comment in the cache about a minor inefficiency re: WriteInvalidate.
2014-10-29mem: have WriteInvalidate obsolete MSHRsCurtis Dunham
Since WriteInvalidate directly writes into the cache, it can create tricky timing interleavings with reads and writes to the same cache line that haven't yet completed. This patch ensures that these requests, when completed, don't overwrite the newer data from the WriteInvalidate.
2014-09-02syscall_emul: add retry flag to SyscallReturnSteve Reinhardt
This hook allows blocking emulated system calls to indicate that they would block, but return control to the simulator so that the simulation does not hang. The actual retry functionality requires additional support, to be provided in a future changeset.
2014-10-22syscall_emul: minor style fix to LiveProcess constructorSteve Reinhardt
2014-10-22syscall_emul: devirtualize BaseBufferArg methodsSteve Reinhardt
Not clear why they were marked virtual to begin with, but that doesn't appear to be necessary.
2014-10-22syscall_emul: Put BufferArg classes in a separate header.Steve Reinhardt
Move the BufferArg classes that support syscall buffer args (i.e., pointers into simulated user space) out of syscall_emul.hh and into a new header syscall_emul_buf.hh so they are accessible to emulated driver implementations. Take the opportunity to add some comments as well.
2014-10-22syscall_emul: add EmulatedDriver objectSteve Reinhardt
Fake SE-mode device drivers can now be added by deriving from this abstract object.
2014-10-22sim: revert 6709bbcf564dNilay Vaish
The identifier SYS_getdents is not available on Mac OS X. Therefore, its use results in compilation failure. It seems there is no straight forward way to implement the system call getdents using readdir() or similar C functions. Hence the commit 6709bbcf564d is being rolled back.
2014-10-20x86: Fixes to avoid LTO warningsAndreas Hansson
This patch fixes a few minor issues that caused link-time warnings when using LTO, mainly for x86. The most important change is how the syscall array is created. Previously gcc and clang would complain that the declaration and definition types did not match. The organisation is now changed to match how it is done for ARM, moving the code that was previously in syscalls.cc into process.cc, and having a class variable pointing to the static array. With these changes, there are no longer any warnings using gcc 4.6.3 with LTO.
2014-10-20misc: Use gmtime for conversion to UTC to avoid getenv/setenvAndreas Hansson
This patch changes how we turn time into UTC. Previously we manipulated the TZ environment variable, but this has issues as the strings that are manipulated could be tainted (see e.g. CERT ENV34-C). Now we simply rely on the built-in gmtime function and avoid touching getenv/setenv all together.
2014-10-20mem: Fix DRAM activationlLimit bugOmar Naji
Ensure that we do the proper event scheduling also when the activation limit is disabled.
2014-10-20base: Fix for stats node on gcc < 4.6.3Andreas Hansson
This patch adds an explicit function to get the underlying node as gcc 4.6.1 and 4.6.2 have issues otherwise.
2014-10-20ext: Bump DRAMPower to avoid compilation issuesAndreas Hansson
This patch bumps DRAMPower to commit 19433a6897ede4bbb19b06694faa8589b5a6569a which contains a small fix for clang, and a work-around for LTO with gcc 4.6.
2014-10-20mem: Add DRAM device size and check against configOmar Naji
This patch adds the size of the DRAM device to the DRAM config. It also compares the actual DRAM size (calculated using information from the config) to the size defined in the system. If these two values do not match gem5 will print a warning. In order to do correct DRAM research the size of the memory defined in the system should match the size of the DRAM in the config. The timing and current parameters found in the DRAM configs are defined for a DRAM device with a specific size and would differ for another device with a different size.
2014-10-20stats: updates due to previous mmap and exit_group patches.Nilay Vaish
2014-10-20cpu: o3: corrects base FP and CC register index in removeThread()Nilay Vaish
2014-10-20sim: invalid alignment checks in mmap and mremapTom Jablin
Presently, the alignment checks in the mmap and mremap implementations in syscall_emul.hh are wrong. The checks are implemented as: if ((start % TheISA::PageBytes) != 0 || (length % TheISA::PageBytes) != 0) { warn("mmap failing: arguments not page-aligned: " "start 0x%x length 0x%x", start, length); return -EINVAL; } This checks that both the start and the length arguments of the mmap syscall are checked for page-alignment. However, the POSIX specification says: The off argument is constrained to be aligned and sized according to the value returned by sysconf() when passed _SC_PAGESIZE or _SC_PAGE_SIZE. When MAP_FIXED is specified, the application shall ensure that the argument addr also meets these constraints. The implementation performs mapping operations over whole pages. Thus, while the argument len need not meet a size or alignment constraint, the implementation shall include, in any mapping operation, any partial page specified by the range [pa,pa+len). So the length parameter should not be checked for page-alignment. By contrast, the current implementation fails to check the offset argument, which must be page aligned. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-10-20sim: mmap: correct behavior for fixed addressMichael Adler
Change mmap fixed address request to return an error if the mapping is impossible due to conflict instead of what I believe used to be silent corruption. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-10-20sim: implement getdents/getdents64 in user modeMichael Adler
Has been tested only for alpha. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-10-20x86: syscall: implementation of exit_groupSeverin Wischmann ext:(%2C%20Ioannis%20Ilkos%20%3Cioannis.ilkos09%40imperial.ac.uk%3E)
On exit_group syscall, we used to exit the simulator. But now we will only halt the execution of threads that belong to the group. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-10-16mem: Modernise PhysicalMemory with C++11 featuresAndreas Hansson
Bring the PhysicalMemory up-to-date by making use of range-based for loops and vector intialisation where possible.
2014-10-16misc: Move AddrRangeList from port.hh to addr_range.hhAndreas Hansson
The new location seems like a better fit. The iterator typedefs are removed in favour of using C++11 auto.
2014-10-16ext: Update fputils to rev 6a47fd8358Andreas Sandberg
This patch updates fputils to the latest revision (6a47fd8358) from the upstream repository (github.com/andysan/fputils). Most notably, this includes changes that export a limited set of 64-bit float manipulation and avoids a warning about unused 64-bit floats in clang.
2014-10-16dev: refactor pci config space for sysfs scanningGeoffrey Blake
Sysfs on ubuntu scrapes the entire PCI config space when it discovers a device using 4 byte accesses. This was not supported by our devices, in particular the NIC that implemented the extended PCI config space. This change allows the extended PCI config space to be accessed by sysfs properly.
2014-10-16mem: Add ExternalMaster and ExternalSlave portsAndrew Bardsley
This patch adds two MemoryObject's: ExternalMaster and ExternalSlave. Each object has a single port which can be bound to an externally- provided bridge to a port of another simulation system at initialisation.