| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2009-04-19 | Memory: Rename LOCKED for load locked store conditional to LLSC. | Gabe Black | |
| 2009-04-19 | SE mode: Make keeping track of the number of syscalls less hacky. | Gabe Black | |
| 2009-04-19 | X86: Actually put the PCI INTA entry into the MP tables. | Gabe Black | |
| 2009-04-19 | X86: Mask the PIC at startup to avoid a glitch which causes an NMI. | Gabe Black | |
| 2009-04-19 | X86: Make E820 report nice, round (and correct) numbers. | Gabe Black | |
| 2009-04-19 | X86: Actually handle 16 bit mode modrm. | Gabe Black | |
| 2009-04-19 | X86: Make the TEST instruction set all the flags it's supposed to. | Gabe Black | |
| 2009-04-19 | X86: Implement broadcast IPIs. | Gabe Black | |
| 2009-04-19 | X86: Fix the ordering of the vendor string reported by CPUID. | Gabe Black | |
| 2009-04-19 | X86: Keep track of what the initial count value was in the LAPIC timer. | Gabe Black | |
| 2009-04-19 | X86: Only recognize the first startup IPI after INIT or reset. | Gabe Black | |
| 2009-04-19 | X86: Use recvResponse to implement the idle bit in the Local APIC ICR. | Gabe Black | |
| 2009-04-19 | X86: Add a function which gets called when an interrupt message has been ↵ | Gabe Black | |
| delivered. | |||
| 2009-04-19 | X86: Fix the flags for interrupt response messages. | Gabe Black | |
| 2009-04-19 | X86: Explicitly use the right width in a few places that need a 64 bit value. | Gabe Black | |
| 2009-04-19 | X86: Keep track of the pioAddr for the local APIC. | Gabe Black | |
| 2009-04-19 | X86: Implement far jmp. | Gabe Black | |
| 2009-04-19 | X86: Some segment selectors can be used when "NULL". | Gabe Black | |
| 2009-04-19 | X86: Fix a bug in the chks microop where it ignored that it found a fault. | Gabe Black | |
| 2009-04-19 | X86: Make the interrupt entering microcode record the value to use, not ↵ | Gabe Black | |
| actually use it. | |||
| 2009-04-19 | X86: LEA calculates an address before segmentation. | Gabe Black | |
| 2009-04-19 | X86: Implement the save machine status word instruction (SMSW). | Gabe Black | |
| 2009-04-19 | X86: Implement the load machine status word instruction (LMSW). | Gabe Black | |
| 2009-04-19 | X86: Update the stats for the fix for CPUID. | Gabe Black | |
| 2009-04-19 | X86: Only use %eax to select a function and look like we support sse2. | Gabe Black | |
| 2009-04-19 | X86: Fix the mov to segment selector in real mode instruction microcode. | Gabe Black | |
| 2009-04-19 | X86: The startup IPI delivery mode is not reserved. | Gabe Black | |
| 2009-04-19 | X86: Implement the STARTUP IPI. | Gabe Black | |
| 2009-04-19 | X86: Implement the INIT IPI. | Gabe Black | |
| 2009-04-19 | X86: Fix the halt microop. | Gabe Black | |
| 2009-04-19 | X86: Start implementing the interrupt command register in the local APIC. | Gabe Black | |
| 2009-04-19 | X86: Make code that sends an interrupt from the IO APIC available for IPIs. | Gabe Black | |
| 2009-04-19 | X86: Automatically make the IO APIC in an N CPU system have id N+1. | Gabe Black | |
| 2009-04-19 | CPU: If the simple CPU is already idle, just return from suspendContext, ↵ | Gabe Black | |
| don't assert. | |||
| 2009-04-19 | X86: Condense the startupCPU code. | Gabe Black | |
| 2009-04-19 | X86: Set the local APIC ID to something meaningful. | Gabe Black | |
| 2009-04-19 | X86: Don't pretend to be an AMD CPU any more. We're not good enough at it. | Gabe Black | |
| 2009-04-18 | o3-mips-regress: add hello word regression. | Korey Sewell | |
| 2009-04-18 | mips-tlb-fix: check for alignment faults.\nMIPS was never updated to use ↵ | Korey Sewell | |
| TLBS correcty in SE mode. The error was forwarding translations directly to pageTable. The TLB should check for alignment faults at bare minimum here but in the long run we should be using TLBs in SE mode for MIPS. | |||
| 2009-04-18 | mips-syscall: mark with correct flag. \nMIPS was using wrong serialization ↵ | Korey Sewell | |
| flag on syscall instructions allowing O3 to handle SE mode syscalls incorrectly and speculate on instructions after a syscall | |||
| 2009-04-18 | o3-delay-slot-bpred: fix decode stage handling of uncdtl. branches.\n decode ↵ | Korey Sewell | |
| stage was not setting the predicted PC correctly or passing that information back to fetch correctly | |||
| 2009-04-18 | mips-shadowsets: fix calcuations. \n Remove Shadowsets from Int & Arch. Reg ↵ | Korey Sewell | |
| Calculations | |||
| 2009-04-17 | o3, inorder: fix FS bug due to initializing ThreadState to Halted. | Steve Reinhardt | |
| For some reason o3 FS init() only called initCPU if the thread state was Suspended, which was no longer the case. There's no apparent reason to check, so I whacked the test completely rather than changing the check to Halted. The inorder init() was also updated to be symmetric, though the previous code was just a fancy no-op. | |||
| 2009-04-15 | o3: handle fetch with no active threads correctly. | Steve Reinhardt | |
| This situation can arise now on the first fetch cycle after the last active thread is halted. It seems easy enough to deal with when it happens rather than trying to avoid it. | |||
| 2009-04-15 | o3: fix {read,set}ArchFloatReg* functions. | Steve Reinhardt | |
| Register indices were not being calculated properly. | |||
| 2009-04-15 | ThreadState: initialize status to Halted in constructor. | Steve Reinhardt | |
| This provides a common initial status for all threads independent of CPU model (unlike the prior situation where CPUs initialized threads to inconsistent states). This mostly matters for SE mode; in FS mode, ISA-specific startupCPU() methods generally handle boot-time initialization of thread contexts (since the right thing to do is ISA-dependent). | |||
| 2009-04-15 | Update stats after elimination of Unallocated state. | Steve Reinhardt | |
| Somehow ending threads with halt() instead of deallocate() reduces the squash count on o3 by 1 (and a few other similarly trivial changes). | |||
| 2009-04-15 | Get rid of the Unallocated thread context state. | Steve Reinhardt | |
| Basically merge it in with Halted. Also had to get rid of a few other functions that called ThreadContext::deallocate(), including: - InOrderCPU's setThreadRescheduleCondition. - ThreadContext::exit(). This function was there to avoid terminating simulation when one thread out of a multi-thread workload exits, but we need to find a better (non-cpu-centric) way. | |||
| 2009-04-15 | configs: Allow M5_CPU2000 env var to set CPU2K binary path. | Steve Reinhardt | |
| It would be nice to have a more comprehensive mechanism but this is a big improvement over manually editing the script. | |||
| 2009-04-13 | X86: Fix minor bug in the page table walker from TLB shuffling. | Gabe Black | |
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