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2018-09-17config, arm, power: Example to report the power for the L2 CacheSherif Elhabbal
This patch add an example to demonstrate how to report the power for the L2 Cache of the big cluster separately ,it decouples the L2 contributions from the CPU power equation Signed-off-by: Sherif Elhabbal <elhabbalsherif@gmail.com> Change-Id: Idde43c8bcb10df9d44d20282eaf21ce87a9d3f58 Reviewed-on: https://gem5-review.googlesource.com/12684 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-09-14power: Add a clock_period variable to power expressionsSherif Elhabbal
Currently 'Clock period in ticks' stat is not accessible in power equations . This patch adds a variable 'clock_period' to be referenced to get the Clock period in ticks Signed-off-by: Sherif Elhabbal <elhabbalsherif@gmail.com> Change-Id: Icac6a2e2003ed75d1680180e53343b0203139d72 Reviewed-on: https://gem5-review.googlesource.com/12664 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-13Fix SConstruct for asan buildEarl Ou
Sometimes it's easier to debug gem5 built with ASan enabled. This CL fixes some build error when using --with-asan. Bug: None Test: ./scripts/build_gem5 --with-asan --with-ubsan build/ARM/gem5.debug Change-Id: Iaaaaebc3f25749e11f97bf454ddd0153b3de56e7 Reviewed-on: https://gem5-review.googlesource.com/12511 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-09-13arch-arm: Correction for address size in EL1&0 translationAnouk Van Laer
When doing EL0/1 translation in stage2, the physical address size will be defined by the hypervisor (via VTCR_EL2.ps, not TCR.ips). See D10.2.121 of the ARM ARM. Change-Id: Ic7df97c0f5950a648f7408cde3955a640b562c1d Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12552 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-09-13arch-arm: Correction to address size in EL2/EL3Anouk Van Laer
This commit corrects how the address size is determined in EL2/EL3. Previously, TCR_ELx.ips was used but this should be TCR_ELx.ps. Change-Id: I7e5a2f376335532a1d1c8c74d12a416617474ae2 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12551 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-09-13mem-cache: Fix bug in handleAtomicReqMissNikos Nikoleris
"4976ff5 mem-cache: Refactor the recvAtomic function" introduced a bug where if an atomic request that fills in using the tempBlock it will not evict it when it finishes handling the request as it should. This triggers an assertion. This change fixes this bug. Change-Id: I73c808a7e15237eddb36b5448ef6728f7bcf7fd9 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12644 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-09-12dev-arm: fix build to missing Pl390 to Gicv2 renameCiro Santilli
Change-Id: I6756f2c789aaca410d201aa64147443b66afee39 Reviewed-on: https://gem5-review.googlesource.com/12645 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-12config, dev-arm: Fix UART handling baremetal modeCiro Santilli
fs.py in baremetal mode currently fails for the VExpress_GEM5_V1 platform due to inconsistent UART naming with error message: AttributeError: object 'VExpress_GEM5_V1' has no attribute 'uart' Consistently name keep all UARTs in the Arm platforms in a vector named 'uart' or as a single device named 'uart'. Update the configuration scripts to reflect the fact that 'uart' can be a vector. Change-Id: I20b8dbac794d6a9be19b6ce8c335a097872132fb Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12473 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-12dev-arm: rename Pl390 to GicV2Ciro Santilli
The Pl390 model has evolved and acquired a lot of the features from GICv2, which means that the name is no longer appropriate. Rename it to GICv2 since this is more representative of the supported features. GICv2 is backwards compatible with the older Pl390, so we decided to simply rename the class to represent both GICv2 and older interfaces such as the instead of creating a new separate one. Change-Id: I1c05fba8b3cb5841c66480e9f05b8c873eba3229 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12492 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-12dev-arm: improve Pl390 parametersCiro Santilli
Remove default dist_addr and cpu_addr register addresses since those are purely platform specific. Parametrize the cpu_size parameter. RealViewPBX has the Gic CPU and distributor base too close for the newer CPU size of 0x2000, leading to overlap. This was introduced in I90a9f669a46a37d79c6cc542087cf91f2044f104 and makes using RealViewPBX fail with: fatal: system.membus has two ports responding within range [0x1f000100 : 0x1f0020ff]: system.realview.gic.pio system.realview.gic.pio Change-Id: Ic6c0e6b3d4705ff369eb739d54a1173a47819b7d Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12491 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-12cpu: Replace the fastmem with a new CPU modelAndreas Sandberg
The AtomicSimpleCPU used to be able to access memory directly to speed up simulation if no caches are used. This is fine as long as no switching between CPU models is required. In order to switch to a new CPU model that requires caches, we currently need to checkpoint the system and restore it into a new configuration. The new 'atomic_noncaching' memory mode provides a solution that avoids this issue since caches are bypassed in this mode. This changeset removes the old fastmem option from the AtomicSimpleCPU and introduces a new CPU, NonCachingSimpleCPU, which derives from the AtomicSimpleCPU. The NonCachingSimpleCPU uses the same mechanism as the AtomicSimpleCPU used to use when accessing memory in when fastmem was enabled. This changeset also introduces a new switcheroo test that tests switching between a NonCachingSimpleCPU and a TimingSimpleCPU with caches. Change-Id: If01893f9b37528b14f530c11ce6f53c097582c21 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12419 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-09-11systemc: Adjust some whitespace in a print out.Gabe Black
This makes a test output file diff successfully. Change-Id: Ia269b4b33f719a2559197d9296f9acc601ec65f7 Reviewed-on: https://gem5-review.googlesource.com/12062 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Make verify.py ignore another warning.Gabe Black
Also make warning filters more general and easier to add by writing a function to generate them. Change-Id: I8d813ded9ad8a9ccac4e48e5ea80a3c9c23959da Reviewed-on: https://gem5-review.googlesource.com/12061 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Make verify.py compare non output log reference files.Gabe Black
There are only a few of these which are vcd files. If there are reference files which aren't the log and which aren't in the gem5 output directory, mark those tests as failed as well. Change-Id: I2c880c13d0f90ccf16ac0439dbac68de9223cc90 Reviewed-on: https://gem5-review.googlesource.com/12060 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Delete empty/misnamed test reference file.Gabe Black
The name of the reference file doesn't match the name of the test, and is empty. There's also a correctly named log file in the same directory which will be used instead. Change-Id: I6501b465b99af403ae4af6d43189280c4b45fc8f Reviewed-on: https://gem5-review.googlesource.com/12059 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Remove some junk test reference files.Gabe Black
These files have truncated names, and are identical to correct versions of the log files. Change-Id: I1e5e3c8c489d41dea21f62b4664b05bf6a742117 Reviewed-on: https://gem5-review.googlesource.com/12058 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Ensure the terminated event is notified in all cases.Gabe Black
The terminated event was being notified if a process was killed, but not if it was terminated in other ways. This change moves the notification into the helper which sets termination related state. Change-Id: I10aa5ad25875db992c8408dc60f087efc76b336b Reviewed-on: https://gem5-review.googlesource.com/12057 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Make verify.py delete obsolete diff files.Gabe Black
If diff file exists but the underlying diff has been fixed, delete the diff file. Change-Id: Icadc21a61c084198a8a246ab6d00a9b885647cde Reviewed-on: https://gem5-review.googlesource.com/12056 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Make verify.py ignore a warning.Gabe Black
Change-Id: Ia887b7195d84d0ba9e77370d7b928e201ca78731 Reviewed-on: https://gem5-review.googlesource.com/12055 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Teach verify.py to diff files when checking test results.Gabe Black
Currently it just diffs the stdout and ignores other reference files. It also doesn't filter out noise in the diffs from non test related simulator messages. These include startup messages, messages when the simulator finishes executing, and some non-standard warnings, etc. Change-Id: Idcb19edd893cd8818423c2c5ebb6cbfb278baffa Reviewed-on: https://gem5-review.googlesource.com/12054 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Add return code verification to verify.py.Gabe Black
This just checks whether gem5 exited of its own accord with a successful error code, or in other words that it didn't hang or crash. More checking will need to be added to verify the output against the golden reference. Change-Id: I1ddef56aa73b5f700743830bd6212804531c484f Reviewed-on: https://gem5-review.googlesource.com/12053 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Record the test's return code in the output directory.Gabe Black
verify.py will be able to use that value later to determine whether a test was successful. Change-Id: Ib499a4b6f202ee46e66e5de1b61a7e6309df9886 Reviewed-on: https://gem5-review.googlesource.com/12052 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Extend the execute phase of verify.py.Gabe Black
Add -j and --timeout options to the execute phase of verify.py. The --timeout option is implemented using the timeout utility program which is assumed to be available on the host system. Python 3.3 added a timeout argument to the subprocess module which is an alternative approach, but then we would be dependent on python 3.3. -j is implemented using the standard multiprocess.pool.ThreadPool class. Change-Id: I15b92f2b14de6710e2027a6a19984b2644b2a8df Reviewed-on: https://gem5-review.googlesource.com/12051 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Detect a process control corner case and report an error.Gabe Black
This error reporting results in an exception being thrown, and one (or more) of the tests depend on that behavior. Change-Id: I858aa14fbb80b0648392179a6a8d2055c91aedf8 Reviewed-on: https://gem5-review.googlesource.com/12050 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Adjust process status tracking to improve kill/reset support.Gabe Black
This change rearranges how process status is tracked so that the kill and reset mechanisms work in more circumstances and more like they're supposed to according to the spec. This makes another test or two pass. Change-Id: Ie2a683a796155a82092109d5bb45f07c84e06c76 Reviewed-on: https://gem5-review.googlesource.com/12049 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Implement most of the sc_report_handler mechanism.Gabe Black
This doesn't include support for the deprecated integer message ids. Change-Id: I309d58df1cdc464428189eb0b7180edf41ca4f67 Reviewed-on: https://gem5-review.googlesource.com/12048 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Ignore direct requests to mark a process as ready.Gabe Black
That might happen when a process is being marked as ready at the start of simulation. Because the process might not end up on the ready list, displacing it from the init list, excplicitly pop it off the init list as well. Change-Id: Iebf972e3e1baedec17b9b99b4da9dd44cd8e6957 Reviewed-on: https://gem5-review.googlesource.com/12047 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Fill out process handle kill and reset mechanisms.Gabe Black
Some flags were being updated too early, making the functions think what they were about to do had already been done. Also, actually check for and throw the exception installed in a process when it's next supposed to run, and when injecting an exception schedule that other process to run immediately. Change-Id: I0856b69903699b2c66f9dc7f44942bbfe3cfdcc4 Reviewed-on: https://gem5-review.googlesource.com/12046 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Fix a "problem" with kill/reset exceptions.Gabe Black
Despite what it says in the spec, the proc_ctrl compliance test throws a copy of the reset exception it catches, not the original. Because of that, the code in the kernel which catches the exception gets the base class, not the derived class with overridden virtual methods, etc. This happens to work for the Accellera implementation because they manipulate members of the base class itself which are preserved despite this bug. To make the test work, we imitate their implementation, even though it exposes more implementation details through the header files. Change-Id: I7ed9818c0552869ec790cb7f7bfbe365ade5e49c Reviewed-on: https://gem5-review.googlesource.com/12045 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Implement much of sc_spawn.Gabe Black
This doesn't implement reset signals, although those aren't implemented for static processes either yet. Change-Id: I748a7f75b9b91774c91d969bc1ff5b07e1711aa3 Reviewed-on: https://gem5-review.googlesource.com/12044 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Promote some functions to sc_export_base.Gabe Black
There are a few functions which return a generic sc_interface pointer which were (in the spec) defined to be in the interface type specific sc_export class. They don't need to be and aren't in the Accellera implementation, and without having them in the base class there's no good way to get at a generic interface pointer from an export. Change-Id: Iba692c79bf1d4f7684f28447d8b22c88ef4b804d Reviewed-on: https://gem5-review.googlesource.com/12043 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Add a sensitivity type for exports.Gabe Black
Dynamic processes can be sensitive to exports, so we need a pending sensitivity to represent them. Change-Id: I87952f8bbb7847ad1f1d98d35cd5dd488e7b28ab Reviewed-on: https://gem5-review.googlesource.com/12042 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Make some functions of the kernel static.Gabe Black
This makes it possible to call them without having to have a kernel instance available. The kernel is a singleton anyway, so there should only ever be a single instance of any of these values. Change-Id: I3610d60cc72e9f3114997fe63db94b96ccaac3cd Reviewed-on: https://gem5-review.googlesource.com/12041 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Implement + and - for sc_time, and sc_max_time.Gabe Black
Change-Id: I294b63840e42e2afdef198229adc60ddbb60b9a1 Reviewed-on: https://gem5-review.googlesource.com/12040 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Fix a couple memory errors.Gabe Black
Because events are held in vectors, it doesn't make sense to keep an iterator into the parent to keep track of where that event is for easy removal since the iterator becomes invalid when the vector is changed. The events need to be stored in a vector because systemc defines an accessor which returns that vector, and building a vector on the fly would be cumbersome. Also, make sure the Event parent pointer is set to nullptr if there isn't a parent. Change-Id: I63a676190e7747e60baaca50009161d47bfc1c54 Reviewed-on: https://gem5-review.googlesource.com/12039 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Implement the SC_EXIT_ON_STARVATION exit mode.Gabe Black
This mode implies checking whether there's any activity left either before starting a delta cycle, or processing delta or timed notification or timeout. Change-Id: I0780a1f720cf63f3d2907b8dd28685266b52d6b4 Reviewed-on: https://gem5-review.googlesource.com/12038 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Fix the time resolution when constructing an sc_time.Gabe Black
This is (sort of) mandated by the spec. More specifically the spec says that the systemc API for changing the time resolution can only be called once, and can only be called before a non-zero sc_time is constructed. Because sc_time can be constructed during elaboration and the gem5 version of time resolution is generally not locked down until the actual simulation starts (after elaboration), the sc_time constructor needs to call the fixing function itself to ensure that, for instance, the scaling factors for various real life time units within gem5 are initialized. Change-Id: Ied4b43659834761b55b5ae49ea62779af891d9e3 Reviewed-on: https://gem5-review.googlesource.com/12037 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Handle event notifications scheduled before sc_start.Gabe Black
After sc_start is called, gem5 has run far enough to have an event queue to schedule the notification events on. Before then, it's still legal to request a timed notification. The scheduler should keep track of those requests, and once an event queue is available it should add them to it. Change-Id: Ie7445b1f2e616f4bd36044a09dbef9e1d12d7350 Reviewed-on: https://gem5-review.googlesource.com/12036 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Make orphans top level objects instead of panic-ing.Gabe Black
When a simulation ends, the sc_objects it contains are destroyed one by one, not necessarily in hierarchy order. That means that a parent object can legitimately be destroyed before its children. Instead of panic-ing when that inevitably happens, this change makes gem5 turn those children into top level objects. Change-Id: Icad9c99310fbc3ddcadbbb4f8a990b4fbfe35bdf Reviewed-on: https://gem5-review.googlesource.com/12035 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Implement some of the basics of sc_time.Gabe Black
This is a very incomplete implementation, but is enough to unblock implementing some other dependent features. Change-Id: Ibd2f3476fe01389e277c6956d48337f551d14acd Reviewed-on: https://gem5-review.googlesource.com/12034 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Implement the various sc_module stage callbacks.Gabe Black
This change also gets rid of the SystemC namespace which was deprecated in favor of sc_gem5. A few utility functions which check whether certain callbacks have finished were also implemented. status tracking moved from a global variable in sc_main.cc to a member of the kernel simobject. Change-Id: I50967fae9c576fbe45b1faff587aaa824857a289 Reviewed-on: https://gem5-review.googlesource.com/12033 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11base: Avoid dividing by zero in Time::[gs]etTick.Gabe Black
Those functions used the value SimClock::Int::ns which, if the time resolution is larger than 1ns, can/will be zero. That will make getTick always return zero, and setTick divide by zero. This change modifies those functions so that the math they do avoids using any integer Ticks per time unit value except for Frequency. It seems unlikely that the Ticks will increment at less than 1Hz. Change-Id: I5cc9db14699c00dcbff48e4593b98522b13b4ccd Reviewed-on: https://gem5-review.googlesource.com/12573 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11base: Correct a small typo in sim/core.(hh|cc).Gabe Black
The value GHz with a small z was spelled GHZ with a large z, which was inconsistent with the other frequency-like values in that namespace. Change-Id: I55dfc447a5811ae584e46769cd9cadd08bd1e716 Reviewed-on: https://gem5-review.googlesource.com/12572 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-11base: Save and restore the width setting of streams used with cprintf.Gabe Black
The flags, precision, and fill character were all being saved and restored, but cprintf might also change the width setting of the stream, and that wasn't being saved or restored and could leak from the cprintf statement. This change adds the code to save and restore that value. Change-Id: Ibedb26f7f538cd3be4fe0462d2ee4e5efd62bc59 Reviewed-on: https://gem5-review.googlesource.com/12571 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-11net: Fix a bug when receiving fragamented packetsPin-Yen Lin
In the previous implementation, the function EtherTap::recvReal will only read one packet when received some ``interrupt'' (explicitly, when async_IO set to true). When someone tries to send a large message to the simulated device, the message will be divided to several packets due to packet fragmentation. In this situation recvReal will only read one packet and left the other packets in the buffer. This significantly increases the networking latency. So before reading from socket, I change the socket into non-blocking mode and keep reading from it until there's no packet left. Change-Id: Ieb94a8532cd3994862b6f3eb9474caf7ccf617da Reviewed-on: https://gem5-review.googlesource.com/12338 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-09-10base: Fix isSubset() for addr ranges with interleavingNikos Nikoleris
This change extends isSubset() which checks whether the range is a subset of an input range to support address ranges with interleaving and hashing. Change-Id: I3dc9ceccb189b7c8665de0355f0555fc2c37d872 Reviewed-on: https://gem5-review.googlesource.com/12319 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-09-10configs: Use the same address ranges for dir and mem_ctrlsNikos Nikoleris
In Ruby, for every directory we create one memory controller for every range in the memory ranges. Previously the memory controllers and the directories created their address ranges independently and as a result a mismatch was possible. In fact, we assinged an interleaved address range with hasing for the memory controllers while the corresponding directories would be assigned the same interleaved address range without hashing. This change uses the address range of the memory controllers to populate the list of address ranges for the corresponding directory and avoid bugs due to code duplication. Change-Id: I1e321c81a254199e5aaa9f3b81f4a4642c60a67a Reviewed-on: https://gem5-review.googlesource.com/12318 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-09-10dev-arm: Make GenericTimer use standard ArmInterruptPinGiacomo Travaglini
This patch is deleting the custom ArchTimer::Interrupt implementation in favour of the standard ArmInterruptPin. Change-Id: I5aa5661e48834398bd7aae15df9578b8db5c8da3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12402 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-10dev-arm: Factory SimObject for generating ArmInterruptPinGiacomo Travaglini
With this patch the python ArmInterruptPin SimObject matches to the C++ ArmInterruptPinGen. The latter is in charge of generating the ArmInterruptPin (which is not a SimObject anymore). This is meant to ease the generation of ArmInterruptPins: by not being SimObjects we are not forced to instantiate them in the configuration script; we can generate them dynamically instead throughout simulation. Change-Id: I917d73a26168447221f5993c8ae975ee3771e3bf Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12401 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-10arm: Use the interrupt adaptor in the PMUAndreas Sandberg
Rewrite interrupt handling in the PMU model to use the new interrupt adaptor. Change-Id: I2cbb99580c46d3e21a1335b897843b7b6e41f10c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12400 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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