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AgeCommit message (Expand)Author
2010-08-25ARM: Implement CPACR register and return Undefined Instruction when FP access...Gabe Black
2010-08-25ARM: Implement all ARM SIMD instructions.Gabe Black
2010-08-25ARM: Expand the mode checking utility functions.Gabe Black
2010-08-25Tracing: Fix trace so 'Predicated False' doesn't show upAli Saidi
2010-08-25mem: fix dumb typo in copyrightsSteve Reinhardt
2010-08-24config: changed ruby config file names to be consistentBrad Beckmann
2010-08-24config: remove ruby's requirement on the timing cmd line paramBrad Beckmann
2010-08-24config: fixed ruby dma device connectionsBrad Beckmann
2010-08-24testers: move testers to a new directoryBrad Beckmann
2010-08-24MOESI_hammer: fixed bug for dma reads in single cpu systemsBrad Beckmann
2010-08-23Faults: Get rid of some commented out code in sim/faults.hh.Gabe Black
2010-08-23X86: Create a directory for files that define register indexes.Gabe Black
2010-08-23Power: Get rid of unused checkFpEnableFault.Gabe Black
2010-08-23ISA: Get rid of old, unused utility functions cluttering up the ISAs.Gabe Black
2010-08-23X86: Get rid of the flagless microop constructor.Gabe Black
2010-08-23X86: Make the TLB fault instead of panic when something is unmapped in SE mode.Gabe Black
2010-08-23X86: Make the x86 ExtMachInst serializable with (UN)SERIALIZE_SCALAR.Gabe Black
2010-08-23X86: Define a noop ExtMachInst.Gabe Black
2010-08-23X86: Mark serializing macroops and regular instructions as such.Gabe Black
2010-08-23X86: Add a .serializing directive that makes a macroop serializing.Gabe Black
2010-08-23X86: Consolidate extra microop flags into one parameter.Gabe Black
2010-08-23CPU: Make the constants for StaticInst flags visible outside the class.Gabe Black
2010-08-23BUILD: GCC 4.4.1/2 have a bug in their auto-vectorizer that we trip onAli Saidi
2010-08-23ALPHA: The previous O3 patch causes a slight stats change with fullsys.Ali Saidi
2010-08-23O3: Skipping mem-order violation check for uncachable loads.Min Kyu Jeong
2010-08-23ARM: Improve printing of uop disassembly.Min Kyu Jeong
2010-08-23ARM: Clean up flattening for SPSR addingMin Kyu Jeong
2010-08-23ARM: Implement DBG instruction that doesn't do much for now.Gene Wu
2010-08-23MEM: Make CLREX a first class request operation and clear locks in caches whe...Gene Wu
2010-08-23ARM: Make sure that software prefetch instructions can't change the state of ...Gene Wu
2010-08-23ARM: Don't write tracedata on writes, it might have been freed already.Gene Wu
2010-08-23ARM: Implement CLREX init/complete acc methodsGene Wu
2010-08-23ARM: Fix Uncachable TLB requests and decoding of xn bitGene Wu
2010-08-23Devices: Allow a device to specify that a request is uncachable.Gene Wu
2010-08-23ARM: For non-cachable accesses set the UNCACHABLE flagGene Wu
2010-08-23ARM: Implement DSB, DMB, ISBGene Wu
2010-08-23ARM: Get SCTLR TE bit from reset SCTLRGene Wu
2010-08-23ARM: Implement CLREXGene Wu
2010-08-23ARM: BX instruction can be contitional if last instruction in a IT blockGene Wu
2010-08-23CPU: Print out flatten-out register index as with IntRegs/FloatRegs traceflagMin Kyu Jeong
2010-08-23CPU: Make Exec trace to print predication result (if false) for memory instru...Min Kyu Jeong
2010-08-23ARM: mark msr/mrs instructions as SerializeBefore/AfterMin Kyu Jeong
2010-08-23O3: Handle loads when the destination is the PC.Min Kyu Jeong
2010-08-23ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.Min Kyu Jeong
2010-08-23ARM: adding genMachineCheckFault() stub for ARM that doesn't panicMin Kyu Jeong
2010-08-23ARM: DFSR status value for sync external data abort is expected to be 0x8 in ...Gene Wu
2010-08-23ARM: Temporary local variables can't conflict with isa parser operands.Gene Wu
2010-08-23ARM: Exclusive accesses must be double word alignedAli Saidi
2010-08-23ARM: Add some registers for big loads/stores to support neon.Ali Saidi
2010-08-23ARM: Decode neon memory instructions.Ali Saidi