index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
Age
Commit message (
Expand
)
Author
2015-02-11
style: Fix broken m5format command
Andreas Sandberg
2015-02-11
style: Fix incorrect style checker option name
Andreas Sandberg
2015-02-11
config: Revamp memtest to allow testers on any level
Andreas Hansson
2015-02-11
stats: Bump the MemTest regression stats
Andreas Hansson
2015-02-11
cpu: Tidy up the MemTest and make false sharing more obvious
Andreas Hansson
2015-02-11
sim: Move the BaseTLB to src/arch/generic/
Andreas Sandberg
2015-02-11
base: Add compiler macros to add deprecation warnings
Andreas Sandberg
2015-02-11
base: Do not dereference NULL in CompoundFlag creation
Andreas Hansson
2015-02-11
dev: Remove unused system pointer in the Platform base class
Andreas Sandberg
2015-02-06
cpu: Idle CPU status logic revised
Alexandru Dutu
2015-02-05
config: rename 'file' var
Steve Reinhardt
2015-02-05
config: make M5_PATH a real search path
Steve Reinhardt
2015-02-03
mem: Clarify express snoop behaviour
Andreas Hansson
2015-02-03
mem: Clarify cache behaviour for pending dirty responses
Andreas Hansson
2015-02-03
base: add an accessor and operators ==,!= to address ranges
Curtis Dunham
2015-02-03
config: Add XOR hashing to the DRAM channel interleaving
Andreas Hansson
2015-02-03
base: Add XOR-based hashed address interleaving
Andreas Hansson
2015-02-03
config: Adjust DRAM channel interleaving defaults
Andreas Hansson
2015-02-03
style: Update the style checker to handle new include order
Andreas Sandberg
2015-02-03
sim: Remove test for non-NULL this in Event
Andreas Sandberg
2015-02-03
dev: Correctly clear interrupts in VirtIO PCI
Andreas Sandberg
2015-02-03
scons: Avoid implicit command dependencies
Andreas Hansson
2014-12-19
sim: prioritize async events; prevent starvation
Curtis Dunham
2015-02-03
cpu: Ensure timing CPU sinks response before sending new request
Andreas Hansson
2015-02-03
config: Fix typo in Float param
Geoffrey Blake
2015-01-30
config: arm: fix os_flags
Malek Musleh
2015-01-25
arm: always set the IsFirstMicroop flag
Ali Saidi
2015-01-25
sim: Clean up InstRecord
Ali Saidi
2015-01-25
cpu: Remove all notion that we know when the cpu is misspeculating.
Ali Saidi
2015-01-25
cpu: Put all CPU instruction tracers in a single file
Ali Saidi
2015-01-25
cpu: remove legion tracer
Ali Saidi
2014-12-23
sim: fix reference counting of PythonEvent
Curtis Dunham
2015-01-22
mem: Remove unused Packet src and dest fields
Andreas Hansson
2015-01-22
mem: Remove Packet source from ForwardResponseRecord
Andreas Hansson
2015-01-22
mem: Remove unused RequestState in the bridge
Andreas Hansson
2015-01-22
mem: Always use SenderState for response routing in RubyPort
Andreas Hansson
2015-01-22
mem: Make the XBar responsible for tracking response routing
Andreas Hansson
2015-01-22
stats: Update stats to reflect x86 table walker changes
Andreas Hansson
2015-01-22
x86: Delay X86 table walk on receiving walker response
Andreas Hansson
2015-01-22
mem: Clean up Request initialisation
Andreas Hansson
2015-01-20
config, ruby: connect dma to network
Malek Musleh
2015-01-20
cpu: commit probe notification on every microop or macroop
Nikos Nikoleris
2015-01-20
scons: Do not build the InOrderCPU
Andreas Hansson
2015-01-20
tests: Remove deprecated InOrderCPU tests
Andreas Hansson
2015-01-20
mem: Fix bug in cache request retry mechanism
Andreas Hansson
2015-01-20
cpu: Fix retry bug in MinorCPU LSQ
Andreas Hansson
2015-01-20
mem: Move DRAM interleaving check to init
Andreas Hansson
2015-01-10
stats: changes due to recent changesets.
Nilay Vaish
2015-01-10
x86 : fxsave and fxrestore missing template code
Emilio Castillo
2015-01-10
cpu: fix RetiredStores probe point
Nikos Nikoleris
[next]