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2006-03-28Use op_decl instead of op_src_decl + op_dest_decl in .isa templates.Steve Reinhardt
The latter causes multiple variable definitions if the same operand is used as both a src and a dest. arch/alpha/isa/mem.isa: arch/mips/isa/formats/mem.isa: Use op_decl instead of op_src_decl + op_dest_decl. The latter causes multiple variable definitions if the same operand is used as both a src and a dest. --HG-- extra : convert_revision : c14d91b293d3afef45c8728d3d8784f372c0b7f4
2006-03-28Make Alpha ItbFault methods abstract instead of calling panic()Steve Reinhardt
(which wasn't working since panic() isn't declared yet here). arch/alpha/faults.hh: Make ItbFault methods abstract instead of calling panic() (which wasn't working since panic() isn't declared yet here). --HG-- extra : convert_revision : b15242baa370777f265a3f6b7d5f5c05702b016f
2006-03-28Make .isa-file ##include file paths relative to including file.Steve Reinhardt
Makes .isa files cleaner and simplifies scanner too. Simplified scanner to work under both old and new versions of scons. arch/SConscript: Simplify .isa scanner... seems to work with both scons 0.96.1 and 0.96.91 now. Assumes .isa ##include paths are relative to including file. arch/alpha/isa/main.isa: arch/mips/isa/formats/formats.isa: arch/mips/isa/main.isa: arch/sparc/isa/formats.isa: arch/sparc/isa/main.isa: Make ##include paths relative to including file. arch/isa_parser.py: Make ##include file paths relative to including file. Makes .isa files cleaner and simplifies scanner too. Partial rewrite of include-handling code to use cool re.sub() feature where you can specify a function to provide the replacement string. Minor cleanup of error-handling code. Also got rid of '#!' at top to make caller choose which python interpreter is used (since SPARC now requires 2.4 to build, we may need to do that via scons in the future). --HG-- rename : arch/mips/isa/formats.isa => arch/mips/isa/formats/formats.isa extra : convert_revision : 15a3920fa3aaf80cd94083eda853aa4e49425045
2006-03-28Merge m5.eecs.umich.edu:/bk/newmemGabe Black
into ewok.(none):/home/gblack/m5/newmem --HG-- extra : convert_revision : 7effd744f9061d4aa8e9c3fa769115dfa73cbb79
2006-03-28SPARC compiles for SE!Gabe Black
arch/sparc/isa/decoder.isa: Replaced register number munging with RdLow and RdHigh operands. arch/sparc/isa/formats/mem.isa: Fixed how the address calculation code is dealt with. arch/sparc/isa/operands.isa: Changed the tabbing so that the whole oeprands block was consistent, and added RdLow and RdHigh operands. These registers are used when Rd is meant to refer to a pair of registers, rather than just one. arch/sparc/isa_traits.hh: Moved some functions to the new (to SPARC) utility.hh file. Also, dummy Fpcr_DepTag and Uniq_DepTag DepTags were added to pacify Tru64. These need to be removed, and Tru64 needs to not be compiled in if it isn't appropriate. arch/sparc/regfile.hh: Changed regSpace to have the correct size. arch/sparc/utility.hh: A new file for sparc to match the one for alpha. --HG-- extra : convert_revision : ff6b529093d15f327ec11f067ad533bacdba9932
2006-03-28Move TLB faults into the normal Fault code. The TLB no longer fills in IPRs ↵Kevin Lim
through its own fault() method; this is handled by the fault's invoke() methods. arch/alpha/faults.cc: Move TLB fault code into the normal fault invoke() method. arch/alpha/faults.hh: Move DTB/ITB fault handling code into their own class with a specific invoke() method. Have DTB/ITB faults derive from these classes. Unfortunately the DtbAlignmentFault is somewhat odd; it's a normal alignment fault, but it must also set some specific IPRs. arch/alpha/tlb.cc: arch/alpha/tlb.hh: Setting IPRs is now handled through the fault itself. --HG-- extra : convert_revision : 5cb92ce2186ff79f632bfcbc9ba62a8a04400eae
2006-03-28Merge m5.eecs.umich.edu:/bk/newmemGabe Black
into ewok.(none):/home/gblack/m5/newmem --HG-- extra : convert_revision : 762df7bf15e8e22a8fab8bbcd933047d1c8cdfa9
2006-03-28Moving towards compilation.Gabe Black
arch/sparc/isa/decoder.isa: Fixed comments so they don't comment out the ending braces of the format specifier. --HG-- extra : convert_revision : 3f037c0a17abd0dff71d22fdcd95959c3670e88a
2006-03-26Add the bus and connector objects to sconsAli Saidi
change getPort parameter from char* to string Add an extra phase between construction and init called connect SConscript: Add the bus and connector objects to scons cpu/simple/cpu.cc: cpu/simple/cpu.hh: the connection to memory shouldn't be made until we know the memory object exists (e.g. after construction) dev/io_device.hh: change to const string mem/bus.hh: change getPort parameter from char* to string initialize num_interfaces mem/mem_object.hh: change getPort parameter from char* to string mem/physical.cc: mem/physical.hh: change getPort parameter from char* to string get rid of the bus object I created last time python/m5/objects/PhysicalMemory.py: get rid of the bus object I created last time sim/main.cc: sim/sim_object.cc: sim/sim_object.hh: Add an extra phase between construction and init called connect --HG-- extra : convert_revision : 0e994f93374fa72a06d291655c440ff1b8e155a9
2006-03-25update for objects having a busAli Saidi
--HG-- extra : convert_revision : 96b5494b7d0b5ca702ac69cfa0bf8c4d44e1cc3b
2006-03-25Implement a very very simple busAli Saidi
requestTime -> time responseTime -> packet.time Make CPU and memory able to connect to the bus dev/io_device.cc: update for request and packet both having a time hand platform off to port for eventual selection of request modes dev/io_device.hh: update for request and packet both havig a time hand platform off to port for eventual selection of request modes mem/bus.hh: Add a device map struct that maps a range to a portId - Which needs work it theory it should be an interval tree - but it is a list and works fine right now Add a function called findPort which returns port for an addr range Add a deviceBlockSize function that really shouldn't exist, but it was easier than fixing the translating port mem/packet.hh: add a time to each packet mem/physical.cc: mem/physical.hh: python/m5/objects/PhysicalMemory.py: Make physical memory take a MemObject parameter of what to connect to mem/request.hh: remove requestTime/responseTime for just time in request which is requset time and the time in the packet which is responsetime python/m5/objects/BaseCPU.py: Instead of memory cpu connects to any memory object python/m5/objects/Bus.py: Fix for new bus object --HG-- extra : convert_revision : 72605e8a3fcdd9e80a41f439909ee7feb3f1fe1d
2006-03-21Merge zizzer:/bk/newmemAli Saidi
into zeep.eecs.umich.edu:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : 45dba22ecbdfc8e1bb0df1efd06a37f40d56b67f
2006-03-21Make PioPort/DmaPort,DmaDevice/PioDevice compile.Ali Saidi
Add another type to the PacketResult enum of Unknown Seperate time into requsetTime and responseTime. dev/io_device.cc: dev/io_device.hh: Make PioPort/DmaPort,DmaDevice/PioDevice compile. mem/packet.hh: Add another type to the PacketResult enum of Unknown (e.g. no state set yet) mem/request.hh: Seperate time into requsetTime and responseTime. --HG-- extra : convert_revision : c6394cb838013296caea6492275252b8cae2882f
2006-03-19Merge zizzer:/bk/newmemKorey Sewell
into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-mips --HG-- extra : convert_revision : db8490e41ec17fc8f4e2dc9548ecdc7d28b4cdd1
2006-03-19support for unaligned memory accessKorey Sewell
arch/mips/isa/base.isa: disassembly fixes arch/mips/isa/decoder.isa: support for unaligned loads/stores arch/mips/isa_traits.hh: edit Syscall Reg values arch/mips/linux_process.cc: call writevFunc on writev syscall --HG-- extra : convert_revision : 4aea6d069bd7ba0e83b23d2d85c50d68532f0454
2006-03-18Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5Steve Reinhardt
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head sim/process.cc: Fix bad auto merge (m5 changes unnecessary in newmem). --HG-- extra : convert_revision : a3ced4cd1668cd47bd02430872ca68b1433aae98
2006-03-18more syscall fixesKorey Sewell
arch/mips/isa_traits.hh: use syscall return function from alpha arch/mips/linux_process.cc: fix some syntax errors, map some functions to the desc. table --HG-- extra : convert_revision : 75e8e8893b7d96bb4fc8e8eced53bd16c0a727d1
2006-03-18Merge zizzer:/bk/newmemKorey Sewell
into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-mips --HG-- extra : convert_revision : 1646b4fb065e3ed9d8de22e3f5c3aa05a2ef01b6
2006-03-18steps toward making syscalls workKorey Sewell
arch/mips/isa/decoder.isa: arch/mips/isa_traits.hh: sim/syscall_emul.cc: make syscall instruction functional arch/mips/linux_process.cc: add all MIPS/Linux syscalls to descriptor list --HG-- extra : convert_revision : 5455a345e76be921e9f63b248aef874b6358e465
2006-03-17Fixed a couple typosGabe Black
--HG-- extra : convert_revision : 2ffbfc4755e46a119c9709d6a5e9ddc41fde45e0
2006-03-17Merge m5.eecs.umich.edu:/bk/newmemGabe Black
into ewok.(none):/home/gblack/m5/newmem arch/sparc/isa/decoder.isa: Hand merged --HG-- extra : convert_revision : 5d5338602c48be48978972a091c5e93f9dd775aa
2006-03-17An attempt to get byteswap to work accross more machines.Gabe Black
--HG-- extra : convert_revision : 4a73507206cf287a89e1d496b2a08cfd1fafdf4d
2006-03-17Clean up and fix for compilationGabe Black
--HG-- extra : convert_revision : c4e66cd678313f7fe169787cb1bf3e45f114c4fd
2006-03-16clean up condition codes a little bitAli Saidi
put back in Tcc code that was deleted in last merge arch/sparc/isa/bitfields.isa: clean up condition codes a little bit --HG-- extra : convert_revision : c554fd5c3ee8cfd6643f69f8351124a7a4b5d9fa
2006-03-16fix to LiveProcess (this change got deleted somehow)Korey Sewell
--HG-- extra : convert_revision : fe4b7dc5b7d583e1d890648ba98bb0daf722a704
2006-03-16Merge zizzer:/bk/newmemKorey Sewell
into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-mips --HG-- extra : convert_revision : 02fe0b0170348dc6f6a985c15123806088a8c23e
2006-03-16Found and fixed 3 decoder.isa bugs!!! Now the hello_world program runs for a ↵Korey Sewell
while before getting in a infinite loop. It actually "tries" to syscall too, but syscalls aren't implemented just yet arch/mips/faults.cc: more descriptive names for faults (will help future users as well as me!) arch/mips/isa/base.isa: make sure we are printing out "BasicOp" format disassembly instructions as dest,src,src instead of src,src,dest arch/mips/isa/decoder.isa: FIX LW/SW Bug!!!! I was actually loading a byte instead of a word FIX JALR Bug!!!! I was not saving the link address in R31 for this instruction FIX SLL/NOP Bug!!! We now recognize the varying flavors of sll,nop,ehb,& ssnop correctly base/loader/elf_object.cc: change back to original way base/loader/elf_object.hh: change back to original! --HG-- extra : convert_revision : 39b65fba31c1842ac6966346fe8a35816a4231fa
2006-03-16Merge m5.eecs.umich.edu:/bk/newmemGabe Black
into ewok.(none):/home/gblack/m5/newmem arch/sparc/isa/decoder.isa: SCCS merged --HG-- extra : convert_revision : 460843b49bc96b3fbc5897828c23f9cf9b010ae0
2006-03-16Fixups towards compiling.Gabe Black
arch/alpha/types.hh: Moved the DependenceTags enum from types to constants. arch/sparc/faults.cc: arch/sparc/faults.hh: Corrected a misspelling of PriviledgeOpcode and PrivilegedAction. arch/sparc/isa/formats.isa: Fixups towards compiling. Added a few additional instruction formats. --HG-- extra : convert_revision : 4c5506877b71b8a5c8c45db41192cf759cdac374
2006-03-16Don't forget to check in the needed header file for the conditional prefetch ↵Ron Dreslinski
building. --HG-- extra : convert_revision : 2c2562da323fa1249af72af3a89c7666c745ae2b
2006-03-16Add warning for ignored loadable ELF segments.Steve Reinhardt
base/loader/elf_object.cc: Print warning if there are more than two loadable segments. We currently assume there are at most two (text & data), and that's held so far, but it would be nice not to silently ignore others. --HG-- extra : convert_revision : 1b3e693e95ba1210b09528b97819a7fa86426edc
2006-03-15Merge zizzer:/bk/newmemKorey Sewell
into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-mips --HG-- extra : convert_revision : 9bdde9b5bd3049744451eda1134f080b7c4b1b59
2006-03-15implement the Tcc instruction to call syscall.Ali Saidi
arch/sparc/isa/bitfields.isa: the trap field is 7:0 arch/sparc/isa/decoder.isa: add code to in the Tcc instruction to call a syscall arch/sparc/isa_traits.hh: We need the syscall num register --HG-- extra : convert_revision : 0861ec1dd8c7cac57765b22bc408fdffbe63fe2a
2006-03-15Merge zizzer:/z/m5/Bitkeeper/m5Ron Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/m5 --HG-- extra : convert_revision : a4de274ec50821218121ba38f9215f2348262c27
2006-03-15Add support for conditional compiling in of prefetchers.Ron Dreslinski
--HG-- extra : convert_revision : 357554632f102224357c8c3848bc4bc7cbb9dc54
2006-03-15add translations for new sections that are mmapped or when the brkAli Saidi
is changed Add a default machine width parameter Arch based live processes arch/alpha/linux/process.cc: arch/alpha/linux/process.hh: arch/alpha/process.cc: arch/alpha/process.hh: arch/alpha/tru64/process.cc: arch/alpha/tru64/process.hh: arch/mips/linux_process.cc: arch/mips/process.cc: arch/mips/process.hh: arch/sparc/linux/process.cc: arch/sparc/linux/process.hh: arch/sparc/process.cc: arch/sparc/process.hh: configs/test/test.py: python/m5/objects/Process.py: sim/process.cc: sim/process.hh: Architecture based live processes arch/mips/isa_traits.hh: arch/sparc/isa_traits.hh: Add a default machine width parameter mem/port.hh: gcc 4 really wants a virtual destructor sim/byteswap.hh: remove the comment around long and unsigned long even though uint32_t and int32_t are defined. Seems to work with gcc 4 and 3.4.3. sim/syscall_emul.cc: sim/syscall_emul.hh: add translations for new sections that are mmapped or when the brk is changed --HG-- extra : convert_revision : e2f9f228113c7127c87ef2358209a399c30ed5c6
2006-03-15add mips simple test in config directoryKorey Sewell
configs/test/hello_mips: hello world mips binary --HG-- extra : convert_revision : 5a495e1bfb1cbddc0879f8e80c02bd7435a02acb
2006-03-15infinitesimal small baby steps toward MIPS actually workingKorey Sewell
arch/mips/isa/formats/branch.isa: let user know that we alter r31 in disassembly arch/mips/isa_traits.cc: add copyRegs function ... comment out serialize float code for now arch/mips/isa_traits.hh: make FloatRegFile a class ... change values of architectural regs arch/mips/process.cc: change MIPS to Mips base/loader/elf_object.cc: get global pointer initialized to a value base/loader/elf_object.hh: Add global_ptr to elf_object constructor base/loader/object_file.hh: MIPS to Mips base/traceflags.py: SimpleCPU trace flag cpu/simple/cpu.cc: DPRINTF flags for SimpleCPU cpu/static_inst.hh: Add Decoder functions to static_inst.hh --HG-- extra : convert_revision : 0544a8524d3fe4229428cb06822f7da208c72459
2006-03-15Don't access init_regs directly. This does not affect newmem; Steve already ↵Kevin Lim
changed this in newmem. --HG-- extra : convert_revision : 19b1ed0bb2c8bcde72843e62f73635e84adf95b5
2006-03-14Merge zizzer:/bk/newmemKorey Sewell
into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem --HG-- extra : convert_revision : 054833d2f7019b9a1247efc4451ccb143242059d
2006-03-14Minor Sconscript edit ... mips decoder changes ... initialize NNPC and ↵Korey Sewell
output fault name in simple cpu SConscript: Separate Alpha EIO from syscall building for other architectures arch/isa_specific.hh: change MIPS constant to 34k arch/mips/isa/decoder.isa: Allow sll,ssnop,nop, and ehb to be determined through decoder using the different types of default cases arch/mips/isa/formats/branch.isa: Delete debug code arch/mips/isa/formats/noop.isa: add a Nop format arch/mips/isa_traits.hh: use constants instead of enums arch/mips/process.cc: point to the correct header file cpu/simple/cpu.cc: Output the actual fault name sim/process.cc: Inititalize NNPC --HG-- extra : convert_revision : adb0026dfad25b14c98fb03c98bfe9c681bba6f8
2006-03-14Remove unneeded header files.Ron Dreslinski
Add some forward declerations. Fix ordering problem of variables in constructor (see sourceforge) Factor out code from header into _impl file to speed building process (keep cache_builder smaller in size) --HG-- extra : convert_revision : 20087f88f95628af716094e09c2287e09580149e
2006-03-14added *.swpGabe Black
--HG-- extra : convert_revision : 90e4387da5bbe5e3f05c4d25713d6a362c6724e8
2006-03-14Fixed up after a hand merge.Gabe Black
arch/alpha/utility.hh: Got rid of unnecessary extern and static qualifiers, and fixed up the hand merge. arch/sparc/regfile.hh: Fixed up SPARC after a hand merge. --HG-- extra : convert_revision : 56e2d90ddd144f3386dbea50fa96cfc461d46b81
2006-03-14Merge m5.eecs.umich.edu:/bk/newmemGabe Black
into ewok.(none):/home/gblack/m5/newmem cpu/cpu_exec_context.cc: Hand merge --HG-- rename : arch/alpha/registerfile.hh => arch/alpha/regfile.hh extra : convert_revision : bd18966f7c37c67c2bc7ca2633b58f70ce64409c
2006-03-14Moved registerfile.hh to regfile.hhGabe Black
--HG-- rename : arch/alpha/registerfile.hh => arch/alpha/regfile.hh extra : convert_revision : 27df93cd2259dab85057f966c801c0db2cb6f022
2006-03-14Added the sparc regfile.hh to bitkeeperGabe Black
--HG-- extra : convert_revision : 7bc8ca989a4f0225ad5644980c8dbc34b0c0e35f
2006-03-14SPARC clean up towards compilability.Gabe Black
--HG-- extra : convert_revision : 156670995fa61599e763b002cd70f31f19b108d1
2006-03-14Missed this in the float register changeset.Gabe Black
--HG-- extra : convert_revision : 35e967fb39fc16e38da13ab1a093d7d0916cffeb
2006-03-14Moved some full system functions into utility.hhGabe Black
--HG-- extra : convert_revision : dd2cd11213890b30975fdabdf7d9bc4652511434
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