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2016-06-02arm: Rewrite ERET to behave according to the ARMv8 ARMAndreas Sandberg
The ERET instruction doesn't set PSTATE correctly in some cases (particularly when returning to aarch32 code). Among other things, this breaks EL0 thumb code when using a 64-bit kernel. This changeset updates the ERET implementation to match the ARM ARM. Change-Id: I408e7c69a23cce437859313dfe84e68744b07c98 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
2016-06-02arm: Correctly check FP/SIMD access permission in aarch32Andreas Sandberg
The current implementation of aarch32 FP/SIMD in gem5 assumes that EL1 and higher are all 32-bit. This breaks interprocessing since an aarch64 EL1 uses different enable/disable bits. This change updates the permission checks to according to what is prescribed by the ARM ARM. Change-Id: Icdcef31b00644cfeebec00216b3993aa1de12b88 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com> Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
2016-06-02tests: add 'CHANGED' output to pickle viewerCurtis Dunham
Change-Id: I64c69fde8657c273adea69122877c5348a4f867a Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-06-02tests: Only run Ruby tests when testing Ruby targetsAndreas Sandberg
Limit the test configs to Ruby-only configs when testing a Ruby target that isn't MI_example. This avoids re-running configs that has already been tested by the generic (non-Ruby) ISA target. This behavior was the expected behavior prior to switching to the new test framework. Change-Id: I3f138dbf9c7071ce862d1073aaec57c59afbc921 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-06-02style: remove extra newline from white space verifier fix methodGabor Dozsa
Change-Id: I7bce7d1cb04efe20d31445eb67ea5ffd2a4a41f4 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-06-02style: respect per verifier ignores for git commitGabor Dozsa
Change-Id: Id00379bdb17594e627ee49c077fb75f499ea550e Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-06-02style: Move the last bits of file_types.py to the style packageAndreas Sandberg
The commit that refactored the style checkers into a new Python package (style: Refactor the style checker as a Python package) accidentally left a fragment of file_types.py in the old location (util/style.py). This was caused by a race between the commit that moved the file and Nate's commit that added a copyright header to the file. This commit moves the last fragment (the copyright header) and removes the old file. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> --HG-- extra : amend_source : 946f1f6fee034ae79bd50ea7dfc3299a60f070c0
2016-05-31stats: update and fix e273e86a873dCurtis Dunham
2016-05-31arm: Enable LPAE support by defaultAndreas Sandberg
LPAE has been tested with Linux 4.4 and seems to work just fine. Let's enable it by default. Change-Id: Id88c6e3c91ae9c353279d42f2aa1f8a78485bd32 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
2016-05-31arm: Correctly check translation mode (aarch64/aarch32)Andreas Sandberg
According to the ARM ARM (see AArch32.TranslateAddress in the pseudocode library), the TLB should be operating in aarch64 mode if the EL0 is aarch32 and EL1 is aarch64. This is currently not the case in gem5, which breaks 64/32 interprocessing. Update the check to match the reference manual. Change-Id: I6f1444d57c0e2eb5f8880f513f33a9197b7cb2ce Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-05-31scons: Use the new test framework from sconsAndreas Sandberg
Rewrite the SCons script responsible for launching tests to use the new test framework. The biggest visible change after this changeset is that SCons no longer produces a "status" file in test build directories. Instead, it creates a status.pickle file. That file can be inspected using the new tests.py script. Another visible change is that timed out tests are now reported as failed rather than a using a separate summary message. Since the pickle file will remain in the build directory after running tests, it's now possible to convert the test results into other formats. For example: ./tests/tests.py show --format junit -o junit.xml \ `find build/ -name status.pickle` To better facilitate running outside of scons, there is now a set of targets that generate test listings that can be used by the test script. There are currently three targets, quick.list, long.list, and all.list. For example: scons build/ARM/tests/opt/all.list for F in `cat build/ARM/tests/opt/all.list`; do ./tests/tests.py run build/ARM/gem5.opt $F done Change-Id: I2c0f8ca0080d7af737362e198eda4cb3a72e6c36 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-05-31tests: Fix incorrect stat.txt ignore when updating refsAndreas Sandberg
ClassicTest was incorrectly ignoring stats.txt when updating reference statistics. This was caused by ignore rules being applied too aggressively when listing reference files. This changeset splits the ignore rules into two different lists: 1) diff_ignore_files that lists the files that shouldn't be diff:ed using the normal diff tool, and 2) ref_ignore_files which lists files that should be ignored by the test system. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-05-31stats: update for snoop filter tweakCurtis Dunham
--HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-27mem, config: Selective use of snoop filterStephan Diestelhorst
Disable the default snoop filter in the SystemXBar so that the typical membus does not have a snoop filter by default. Instead, add the snoop filter only when there are caches added to the system (with the caches / l2cache options). The underlying problem is that the snoop filter grows without bounds (for now) if there are no caches to tell it that lines have been evicted. This causes slow regression runs for all the atomic regressions. This patch fixes this behaviour. --HG-- extra : source : f97c20511828209757440839ed48d741d02d428f
2016-05-30scons: Bump minimum gcc version to 4.8Andreas Hansson
After reaching consensus on the mailing list, this patch officially makes gcc 4.8 the minimum. A few checks in the SConstruct are cleaned up as a result. This patch also adds "-fno-omit-frame-pointer" when using ASAN (which is part of the gcc/clang recommended flags).
2016-05-27cpu: fix lastStopped unserialisationIlias Vougioukas
MinorCPU fix for corrupt numCycles when resuming from a previous simulation. --- src/cpu/minor/cpu.cc | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)
2016-05-27power: Allow voltage to be configured via cmd lineAkash Bagdia
--- src/python/m5/params.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
2016-05-27scons: Enable override suggestions on gcc 5.0+Matteo Andreozzi
--- SConstruct | 4 ++++ 1 file changed, 4 insertions(+)
2016-05-27arm: Use the target EL state when determining fault formatAndreas Sandberg
We currently check the current state instead of the state of the target EL when determining how we report a fault. This breaks interprocessing since EL0 in aarch32 would report its fault status using the aarch32 registers even if EL1 is in aarch64. Fix this to report the fault using the format of the target EL. Change-Id: Ic080267ac210783d1e01c722a4ddaa687dce280e Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com>
2016-05-26arm: Fix incorrect TLB permission check in aarch32Andreas Sandberg
The TLB currently assumes that the pxn bit in an LPAE page descriptor disables execution from unprivileged mode. However, according to the architecture manual, this bit should disable execution from privileged modes. Update the TLB implementation to reflect this behavior. Change-Id: I7f1bb232d7a94a93fd601a9230223195ac952947 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-05-26arm: Make EL checks available in SE modeAndreas Sandberg
A lot of code assumes that it is possible to test what the highest EL is and if it is 64 bit. These calls currently don't work in SE mode since they rely on an instance of an ArmSystem. Change-Id: I0d1f261926a66ce3dc4fa116845ffb2a081446f2 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
2016-05-26mem: Fix memory leak in handling of deferred snoopsAndreas Hansson
This patch fixes a memory leak where deferred snoop packets never got deallocated. On the call to MSHR::handleSnoop these snoops were treated as if a response will be sent, as the MSHR was pendingModified. Consequently, a copy of the packet was created and added to the MSHR targets. However, an preceeding target to the same MSHR, originally from a CPU, was serviced before the snoop, and caused the block to be invalidated. This happens for ReadExReq and UpgradeReq. Note that the original snoop will receive a response, just not from the cache in question, but instead from the cache upstream that issued the ReadExReq or UpgradeReq. Change-Id: I4ac012fbc8a46cf693ca390fe9476105d444e6f4 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-05-26dev, arm: Add a flag to enable/disable gem5 GIC extensionsAndreas Sandberg
Make it possible to disable gem5 gic extensions by setting the gem5_extensions param to False from Python. Change-Id: Icb255105925ef49891d69cc9fe5cc55578ca066d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Geoffrey Blake <geoffrey.blake@arm.com>
2016-05-26cpu: Add a basic progress check to the TrafficGenAndreas Hansson
This patch adds a progress check to the TrafficGen so that it is easier to detect deadlock scenarios where the generator gets stuck waiting for a retry, and makes no further progress. Change-Id: Ifb8779ad0939f52c0518d0e867bac73f99b82e2b Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
2016-05-26mem: Do not set cacheResponding on MSHR snoop if not respondingAndreas Hansson
This patch changes the flow control for HSHR::handleSnoop to ensure that we only set cacheResponding on the snoop packet if we are actually responding. This avoids situations where a responder is stalling indefinitely on a response that never arrives. Change-Id: I691dd01755b614b30203581aa74fc743b350eacc Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-05-26mem: Fix MemChecker unique_ptr type mismatchAndreas Hansson
This patch fixes the type of the unique_ptr instances, to ensure that the data that is allocated with new[] is also deleted with delete[]. The issue was highlighted by ASAN. Change-Id: I2c5510424959d862a9954d83e728d901bb18d309 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
2016-05-26arm: Fix heap overflow issue in Neon64Load operationAndreas Hansson
This patch fixes an issue identified by ASAN where the Neon64Load operation assumes the packet always contains 16 bytes. Change-Id: If24a7e461d60cb80970dfbe61d923d7d56926698 Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-05-26arm, dev: Remove superfluous loop increment in flash deviceAndreas Hansson
As identified by clang-3.8, there was a superfluous loop increment in the flash device which is now removed. Change-Id: If46a1c4f72d3d4c9f219124030894ca433c790af Reviewed-by: Rene De Jong <rene.dejong@arm.com>
2016-05-26mem: fix headers include order in the cache related classesNikos Nikoleris
Change-Id: Ia57cc104978861ab342720654e408dbbfcbe4b69 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-05-26mem: remove redudant check whether the cache forwards snoopsNikos Nikoleris
Change-Id: I57b56771086e1e2f512977fb7248d93c171ab925 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-05-26mem: change NULL to nullptr in the cache related classesNikos Nikoleris
Change-Id: I5042410be54935650b7d05c84d8d9efbfcc06e70 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-05-26mem: fix the line length in the cache related classesNikos Nikoleris
Change-Id: I6d1feb164a958dde0da87a1cd2698096112c4a82 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-05-26tests: Add test infrastructure as a Python moduleAndreas Sandberg
Implement gem5's test infrastructure as a Python module and a run script that can be used without scons. The new implementation has several features that were lacking from the previous test infrastructure such as support for multiple output formats, automatic runtime tracking, and better support for being run in a cluster environment. Tests consist of one or more steps (TestUnit). Units are run in two stages, the first a run stage and then a verify stage. Units in the verify stage are automatically skipped if any unit run stage wasn't run. The library currently contains TestUnit implementations that run gem5, diff stat files, and diff output files. Existing tests are implemented by the ClassicTest class and "just work". New tests can that don't rely on the old "run gem5 once and diff output" strategy can be implemented by subclassing the Test base class or ClassicTest. Test results can be output in multiple formats. The module currently supports JUnit, text (short and verbose), and Python's pickle format. JUnit output allows CI systems to automatically get more information about test failures. The pickled output contains all state necessary to reconstruct a tests results object and is mainly intended for the build system and CI systems. Since many JUnit parsers parsers assume that test suite names look like Java package names. We currently output path-like names with slashes separating components. Test names are translated according to these rules: * '.' -> '-" * '/' -> '.' The test tool, tests.py, supports the following features: * Test listing. Example: ./tests.py list arm/quick * Running tests. Example: ./tests.py run -o output.pickle --format pickle \ ../build/ARM/gem5.opt \ quick/se/00.hello/arm/linux/simple-timing * Displaying pickled results. Example: ./tests.py show --format summary *.pickle Change-Id: I527164bd791237aacfc65e7d7c0b67b695c5d17c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Joel Hestness <jthestness@gmail.com>
2016-05-19config, x86: Properly space pad the X86IntelMPBus Entry descriptionsBjoern A. Zeeb
According to the Intel Multi Processor Specification rev 1.4 (-006) (*), section 4.3.2 Bus Entries, Bus type strings are >>6-character ASCII (blank-filled) strings<<. This patch properly pads the entries with the missing spaces at the end. (*) http://www.intel.com/design/pentium/datashts/24201606.pdf Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-05-19arm,dev: PL011 UART_FR read status enhancementBjoern A. Zeeb
Given we do not simulate a FIFO currently there are only two states we can be in upon read: empty or full. Properly signal the latter. Add and sort constants for states in the header file. Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-05-19x86, dev: properly space the APIC registersBjoern A. Zeeb
Registers are 0x10 and not 0x8 apart. The latter leads to invalid calculations of index in array which in turn means that we will not find the interrupt we were looking (been notified) for in the OS. Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-05-19dev, virtio: properly set PCI address space to use IOREGBjoern A. Zeeb
VirtIO spec < 1.0 demands IOREG to be used on PCI and not memory mapped. Set the correct bit on the PCI address accordingly. Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-05-16gpu-compute: fix bug in GPUDynInst::isScalarRegister()Tony Gutierrez
2016-05-09scons: Rewrite git style hook installerAndreas Sandberg
The SCons script currently assumes that .git is a proper directory with all git meta data. This isn't the case if the working directory was checked out using git worktrees. In such case .git is a file with meta data telling git where the repository data is stored. This changeset updates changes the SConstruct file to rely on git rev-parse to get the real git directory. Change-Id: I3d0475eabc12e868193797067a88e540a9b6e927 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-05-09tests: Enable test running outside of gem5's source treeAndreas Sandberg
The learning gem5 scripts currently assumes that the current working directory is the root of gem5's source tree. This isn't necessarily the case when running the tests using gem5's new test runner. Change-Id: Ief569bbe77b1b3e2b0fb0e6c575fb0705bbba9b3 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-05-07tests: update EIO ref stats for removed cache statsSteve Reinhardt
Complaints about changes in EIO tests were due to reference files that still have removed cache stats from cset 11454:e55afadc4e19.
2016-05-06gpu-compute: fix spacing in GPUDynInst ctorTony Gutierrez
2016-05-06gpu-compute: fix uninitialized member bug in GPUDynInstTony Gutierrez
the n_reg field in the GPUDynInst is not currently set in the constructor. if it is not set externally, there are assertion failures that may occur if the random value it gets is just right. here we set it to 0 by default.
2016-05-06dev, arm: Update GIC to use GICv2 register namingAndreas Sandberg
The GICv2 has a new and slightly more consistent register naming. Update gem5's GIC register names to match the new documentation. Change-Id: I8ef114eee8a95bf0b88b37c18a18e137be78675a Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-05-06arm: Update dts to work with the new HDLCD driverAndreas Sandberg
The dts files in system/arm/dt currently assume that an (unreleased) gem5-specific virtual encoder is used as a remote endpoint for the HDLCD. This driver won't be released as a more general virtual encoder is about to be posted on the Linux DRI devel list and this encoder has now been merged with gem5's kernel tree. This changeset updates gem5's dts files to use that encoder. Change-Id: Ic1a1be728efd31603752fdfba005b6dbdea42e7e Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Rene De Jong <rene.dejong@arm.com>
2016-04-28scons: emit correct message before installing git hookCurtis Dunham
Change-Id: Ied2e018a9a1b6db446edbaac871ac4efd795ec36 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-04-28style: ignore test data in style checksCurtis Dunham
Change-Id: If797eaf3842b5c1604942bb60f091800ee814a2a Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-04-28style: respect ignores for git commitCurtis Dunham
Previously it ignored the ignores for git but not Mercurial. Change-Id: I178fe879ebd268e863063eb9e30ec87e8ac8faec Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-04-28style: improve compatibility with old git versionsCurtis Dunham
Older versions of git need the '=' to connect --diff-filter to its argument. Change-Id: Ic62057567db061684be88a7c2d80a6a5d4c11dcf
2016-04-28style: Don't include diff context in git style hookAndreas Sandberg
The git style hook currently includes a few lines of diff context when determining changed regions. This is undesirable as this triggers false positives when modifying existing files with a lot of style violations. This change sets the amount of context to 0, which is the default value when requesting staged regions from the git helper. Change-Id: Ibe03123e329ea0241281e104183a68d6c495b190 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>