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2015-07-20slicc: support for multiple message types on the same bufferDavid Hashe
This patch allows SLICC protocols to use more than one message type with a message buffer. For example, you can declare two in ports as such: in_port(ResponseQueue_in, ResponseMsg, responseFromDir, rank=3) { ... } in_port(tgtResponseQueue_in, TgtResponseMsg, responseFromDir, rank=2) { ... }
2015-08-01slicc: fatal->panic on invalid transitionsBrad Beckmann
2015-07-20mem: Hit callback delay fixDavid Hashe
This patch was created by Bihn Pham during his internship at AMD. There is no need to delay hit callback response messages by a cycle because the response latency is already incurred in the Ruby protocol. This ensures correct timing of memory instructions.
2015-07-20cpu: Fixed a bug on where to fetch the next instruction fromDavid Hashe
Figure out if the next instruction to fetch comes from the micro-op ROM or not. Otherwise, wrong instructions may be fetched.
2015-07-20x86: x86 instruction-implementation bug fixesDavid Hashe
Added explicit data sizes and an opcode type for correct execution.
2015-07-20util: added .cl OpenCL extension to file_type.pyBrad Beckmann
2015-07-20util: added .mk makefile extension to file_types.pyBrad Beckmann
2015-07-20ruby: re-added the addressToInt slicc interface functionBrad Beckmann
This helper function is very useful converting address offsets to integers that can be used for protocol specific destination mapping.
2015-07-20syscall: Add readlink to x86 with special case /proc/self/exeDavid Hashe
This patch implements the correct behavior.
2015-07-20ruby: add useful dprints to sequencerBrad Beckmann
Added two data block dprints that are useful when tracking down data check failures in the ruby random tester.
2015-07-20slicc: isinstance bugfixDavid Hashe
This fix prevents spurious errors when searching for a symbol that may be located in one of multiple symbol tables.
2015-07-31util: add a vimrc that matches gem5 style guideAnthony Gutierrez
2015-07-31stats: Update switcheroo reference statsAndreas Sandberg
The Minor draining fixes affect perturb the timing slightly since it affects how the simulator is drained. Update reference statistics to reflect this expected change.
2015-07-31cpu: Update debug message from Fetch1 isDrained() in MinorAndreas Sandberg
Fix a spurious %s and include the state of the Fetch1 stage in the debug printout.
2015-07-31cpu: Fix Minor drain issues when switched outAndreas Sandberg
The Minor CPU currently doesn't drain properly when it is switched out. This happens because Fetch 1 expects to be in the FetchHalted state when it is drained. However, because the CPU is switched out, it is stuck in the FetchWaitingForPC state. Fix this by ignoring drain requests and returning DrainState::Drained from MinorCPU::drain() if the CPU is switched out. This is always safe since a switched out CPU, by definition, doesn't have any instructions in flight.
2015-07-30stats: Bump stats after Minor switcheroo inclusionAndreas Sandberg
2015-07-30tests: Add Minor to the ARM full switcheroo testsAndreas Sandberg
Add the Minor CPU to the RealView and RealView64 full switcheroo tests.
2015-07-30cpu: Only activate thread 0 in Minor if the CPU is activeAndreas Sandberg
Minor currently activates thread 0 in startup() to work around an issue where activateContext() is called from LiveProcess before the process entry point is known. When activateContext() is called, Minor creates a branch instruction to the process's entry point. The first time it is called, the branch points to an undefined location (0). The call in startup() updates the branch to point to the actual entry point. When instantiating a switched out Minor CPU, it still tries to activate thread 0. This is clearly incorrect since a switched out CPU can't have any active threads. This changeset adds a check to ensure that the thread is active before reactivating it.
2015-07-30cpu: Fix drain issues in the Minor CPUAndreas Sandberg
The drain refactor patches introduced a couple of bugs in the way Minor handles draining. This patch fixes an incorrect assert and a case of infinite recursion when the CPU signals drain done.
2015-07-30stats: Update stats for clean eviction additionAndreas Hansson
2015-07-30mem: Add missing clean eviction on uncacheable accessAndreas Hansson
This patch adds a missing clean eviction, occuring when an uncacheable access flushes and invalidates an existing block.
2015-07-30mem: Remove unused RequestCause in cacheAndreas Hansson
This patch removes the RequestCause, and also simplifies how we schedule the sending of packets through the memory-side port. The deassertion of bus requests is removed as it is not used.
2015-07-30mem: Make caches way awareDavid Guillen-Fandos
This patch makes cache sets aware of the way number. This enables some nice features such as the ablity to restrict way allocation. The implemented mechanism allows to set a maximum way number to be allocated 'k' which must fulfill 0 < k <= N (where N is the number of ways). In the future more sophisticated mechasims can be implemented.
2015-07-30mem: Transition away from isSupplyExclusive for writebacksAndreas Hansson
This patch changes how writebacks communicate whether the line is passed as modified or owned. Previously we relied on the isSupplyExclusive mechanism, which was originally designed to avoid unecessary snoops. For normal cache requests we use the sharedAsserted mechanism to determine if a block should be marked writeable or not, and with this patch we transition the writebacks to also use this mechanism. Conceptually this is cleaner and more consistent.
2015-07-30mem: Tidy up CacheBlk classAndreas Hansson
This patch modernises and tidies up the CacheBlk, removing dead code.
2015-07-30mem: Tidy up packetAndreas Hansson
Some minor fixes and removal of dead code. Changing the flags to be enums rather than static const (to avoid any linking issues caused by the latter). Also adding a getBlockAddr member which hopefully can slowly finds its way into caches, snoop filters etc.
2015-07-30stats: Bump stats to match current behaviourAndreas Hansson
Somehow this one seems to have slipped through. Perhaps non-determinism somewhere?
2015-07-30cpu: Fix issue identified by UBSanAndreas Hansson
2015-07-28revert 5af8f40d8f2cNilay Vaish
2015-07-26cpu: implements vector registersNilay Vaish
This adds a vector register type. The type is defined as a std::array of a fixed number of uint64_ts. The isa_parser.py has been modified to parse vector register operands and generate the required code. Different cpus have vector register files now.
2015-07-26cpu: o3: slight correction to identation in rename_impl.hhNilay Vaish
2015-07-24style: change Process function calls to use camelCaseBrandon Potter
The Process class methods were using an improper style and this subsequently bled into the system call code. The following regular expressions should be helpful if someone transitions private system call patches on top of these changesets: s/alloc_fd/allocFD/ s/sim_fd(/simFD(/ s/sim_fd_obj/getFDEntry/ s/fix_file_offsets/fixFileOffsets/ s/find_file_offsets/findFileOffsets/
2015-07-24syscall_emul: standardized file descriptor name and add return checks.Brandon Potter
The patch clarifies whether file descriptors are host file descriptors or target file descriptors in the system call code. (Host file descriptors are file descriptors which have been allocated through real system calls where target file descriptors are allocated from an array in the Process class.)
2015-07-24base: refactor process class (specifically FdMap and friends)Brandon Potter
This patch extends the previous patch's alterations around fd_map. It cleans up some of the uglier code in the process file and replaces it with a more concise C++11 version. As part of the changes, the FdMap class is pulled out of the Process class and receives its own file.
2015-07-24syscall_emul: file descriptor interface changesBrandon Potter
This patch gets rid of unused Process::dup_fd method and does minor refactoring in the process class files. The file descriptor max has been changed to be the number of file descriptors since this clarifies the loop boundary condition and cleans up the code a bit. The fd_map field has been altered to be dynamically allocated as opposed to being an array; the intention here is to build on this is subsequent patches to allow processes to share their file descriptors with the clone system call.
2015-07-24ruby: dma sequencer: removes redundant codeBrandon Potter
2015-07-22ruby: network: NetworkLink inherits from Consumer now.Nilay Vaish
2015-07-21configs: network test: remove redundant physical memoryNilay Vaish
2015-07-18stats: x86: updates due to patch on vexNilay Vaish
2015-07-17x86: decode instructions with vex prefixNilay Vaish
This patch updates the x86 decoder so that it can decode instructions with vex prefix. It also updates the isa with opcodes from vex opcode maps 1, 2 and 3. Note that none of the instructions have been implemented yet. The implementations would be provided in due course of time.
2015-07-15dev: add support for multi gem5 runsGabor Dozsa
Multi gem5 is an extension to gem5 to enable parallel simulation of a distributed system (e.g. simulation of a pool of machines connected by Ethernet links). A multi gem5 run consists of seperate gem5 processes running in parallel (potentially on different hosts/slots on a cluster). Each gem5 process executes the simulation of a component of the simulated distributed system (e.g. a multi-core board with an Ethernet NIC). The patch implements the "distributed" Ethernet link device (dev/src/multi_etherlink.[hh.cc]). This device will send/receive (simulated) Ethernet packets to/from peer gem5 processes. The interface to talk to the peer gem5 processes is defined in dev/src/multi_iface.hh and in tcp_iface.hh. There is also a central message server process (util/multi/tcp_server.[hh,cc]) which acts like an Ethernet switch and transfers messages among the gem5 peers. A multi gem5 simulations can be kicked off by the util/multi/gem5-multi.sh wrapper script. Checkpoints are supported by multi-gem5. The checkpoint must be initiated by a single gem5 process. E.g., the gem5 process with rank 0 can take a checkpoint from the bootscript just before it invokes 'mpirun' to launch an MPI test. The message server process will notify all the other peer gem5 processes and make them take a checkpoint, too (after completing a global synchronisation to ensure that there are no inflight messages among gem5).
2015-07-13mem: Fix (ab)use of emplace to avoid temporary object creationAndreas Hansson
2015-07-13mem: Updated DRAMSim2 wrapper to new drain APIAndreas Hansson
Somehow this one slipped through without being updated.
2015-07-10ruby: replace global g_abs_controls with per-RubySystem varBrandon Potter
This is another step in the process of removing global variables from Ruby to enable multiple RubySystem instances in a single simulation. The list of abstract controllers is per-RubySystem and should be represented that way, rather than as a global. Since this is the last remaining Ruby global variable, the src/mem/ruby/Common/Global.* files are also removed.
2015-07-10ruby: replace global g_system_ptr with per-object pointersBrandon Potter
This is another step in the process of removing global variables from Ruby to enable multiple RubySystem instances in a single simulation. With possibly multiple RubySystem objects, we can no longer use a global variable to find "the" RubySystem object. Instead, each Ruby component has to carry a pointer to the RubySystem object to which it belongs.
2015-07-10ruby: replace g_ruby_start with per-RubySystem m_start_cycleBrandon Potter
This patch begins the process of removing global variables from the Ruby source with the goal of eventually allowing users to create multiple Ruby instances in a single simulation. Currently, users cannot do so because several global variables and static members are referenced by the RubySystem object in a way that assumes that there will only ever be a single RubySystem. These need to be replaced with per-RubySystem equivalents. This specific patch replaces the global var g_ruby_start, which is used to calculate throughput statistics for Throttles in simple networks and links in Garnet networks, with a RubySystem instance var m_start_cycle.
2015-07-10ruby: remove extra whitespace and correct misspelled wordsBrandon Potter
2015-07-07dev, arm: Add a device model that uses the NoMali modelAndreas Sandberg
Add a simple device shim that interfaces with the NoMali model library. The gem5 side of the interface supports Mali T60x/T62x/T760 GPUs. This device model pretends to be a Mali GPU, but doesn't render anything and executes in zero time.
2015-07-07ext: Add the NoMali GPU no-simulation libraryAndreas Sandberg
Add revision 9adf9d6e2d889a483a92136c96eb8a434d360561 of NoMali-model from https://github.com/ARM-software/nomali-model. This library implements the register interface of the Mali T6xx/T7xx series GPUs, but doesn't do any rendering. It can be used to hide the effects of software rendering.
2015-07-07stats: Update pc-switcheroo statsAndreas Sandberg
The pc-switcheroo test cases has slightly different timing after decoupling draining from the SimObject hierarchy. This is expected since objects aren't drained in the exact same order as before.