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2018-05-04scons: Fix --with-ubsan/asan compilation flagsGiacomo Travaglini
SConstruct was using an undefined env variable; this patch uses the main Environment variable. Change-Id: I30ab6b4bbfa6d9a71a30fb33406a799bfb476821 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10181 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-05-03mem-ruby: Consistent dprintf formats for issue outcomesBrad Beckmann
Change-Id: I053fc42f0d5f678f8e3434b53a0f09e00fc3e345 Reviewed-on: https://gem5-review.googlesource.com/10221 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-05-03arch-x86: Enable fstatfs for x86_64Tony Gutierrez
Change-Id: Ic871f852c4892f2228f0d9bb3cc5cb66887d9736 Reviewed-on: https://gem5-review.googlesource.com/10201 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-05-03mem-cache: Create Second-Chance replacement policyDaniel R. Carvalho
Implementation of a Second-Chance replacement policy. Similar to FIFO, but every block is given a second chance if it has been touched. Change-Id: Id4d52b698d0045a4914a4d848fdf9c3c00a28508 Reviewed-on: https://gem5-review.googlesource.com/9441 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-05-03mem-cache: ReplacementPolicy specific replacement dataDaniel R. Carvalho
Replacement data is specific for each replacement policy, and thus should be instantiated differently by each policy. Touch() and reset() do not need to be aware of CacheBlk, as they only update its ReplacementData. Invalidate() makes replacement policies independent of cache blocks, by removing the awareness of the valid state. An inheritable base ReplaceableEntry class was created to allow usage of replacement policies with any table-like structure. Change-Id: I998917d800fa48504ed95abffa2f1b7bfd68522b Reviewed-on: https://gem5-review.googlesource.com/9421 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-05-02arch-x86: implement movntps/movntpd SSE instsSteve Reinhardt
These are non-temporal packed SSE stores. Change-Id: I526cd6551b38d6d35010bc6173f23d017106b466 Reviewed-on: https://gem5-review.googlesource.com/9861 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-05-02x86: Add a ld/st microop flag for marking an access uncacheable.Gabe Black
This percolates down to the memory request object which will have its "UNCACHEABLE" flag set. Change-Id: Ie73f4249bfcd57f45a473f220d0988856715a9ce Reviewed-on: https://gem5-review.googlesource.com/9881 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-05-02arch-x86: Enable the umask system callTony Gutierrez
Change-Id: I309beb1604657e8d1807ac90458709df57f0f819 Reviewed-on: https://gem5-review.googlesource.com/10161 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-04-27sim,cpu,mem,arch: Introduced MasterInfo data structureGiacomo Travaglini
With this patch a gem5 System will store more info about its Masters. While it was previously keeping track of the Master name and Master ID only, it is now adding a per-Master pointer to the SimObject related to the Master. This will make it possible for a client to query a System for a Master using either the master's name or the master's pointer. Change-Id: I8b97d328a65cd06f329e2cdd3679451c17d2b8f6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9781 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-26mem-cache: Use block iteration in BaseSetAssocDaniel R. Carvalho
Use block iteration instead of numSets and assoc in print(), cleanupRefs() and computeStats(). This makes these functions rely solely on what they are used for: printing and calculating stats of blocks. With the addition of Sectors an extra indirection level is added, and thus these functions would be skipping blocks. Change-Id: I0006f82736cce02ba3e501ffafe9236f748daf32 Reviewed-on: https://gem5-review.googlesource.com/10143 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-20docs: Fix power model doxygenJason Lowe-Power
Change-Id: I0a9a30bc4a89411e0f1dd897f0d1f05f20790b50 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/9981 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-04-19mem-cache: Use findBlock in FALRU's block accessDaniel R. Carvalho
An access must perform a block search, which is done by findBlock. The tagHash is indexed by tags, so use extractTag instead of re- implementing its functionality. Change-Id: Ib5abacbc65cddf0f2d7e4440eb5355b56998a585 Reviewed-on: https://gem5-review.googlesource.com/10082 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-04-19mem-cache: Use secure flag in FALRU's findBlockDaniel R. Carvalho
FALRU's findBlock() must use the secure flag to assure proper functionality. Change-Id: I54e9fbd3c9093b3e8043c4c6c850b74a8f1f5ec0 Reviewed-on: https://gem5-review.googlesource.com/10081 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-19arch-arm: Add ARMv8.1 TTBR1_EL2 registerGiacomo Travaglini
This patch adds ARMv8.1 TTBR1_EL2 register into the decodeAArch64SysReg table, but stil leaving it unimplemented (Accessing it through MSR/MRS causes an exception) Change-Id: I463b86cc544233aa1ee5b2fcba689d6b9f2a874b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10063 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-19arch-arm: Fix Unknown Instruction disassembleGiacomo Travaglini
Do not print the entire ExtMachInst when disassembling an Unknown Instruction. Change-Id: Icd5908ec0fa430090165b2426372bdeb43c2a155 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10062 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-19arch-arm: Change disassemble when MSR to UNKNOWN registerGiacomo Travaglini
This patch changes the fault being thrown when MSR/MRS to an unknown Misc register in AArch64. While previously the instruction was decoded as an Unknown instruction (hence not printing any information), it is now decoded as a FailUnimplemented and the unrecognized System register numbers (CRn, op0...) are printed. Change-Id: I205ff7adcde5934231c77e8d2250db69a34581fc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10061 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-18mem-cache: Create NRU Replacement PolicyDaniel R. Carvalho
Implementation of a Not Recently Used replacement policy. Change-Id: I24ab3a6f1db6dcb756b869cfebb5c4bc544170e8 Reviewed-on: https://gem5-review.googlesource.com/9001 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-18arch-arm: Fix masking in CPACR_EL1Chuan Zhu
Some bits in CPACR_EL1 are RES0 but not RAZ/WI. For instance, bit CPACR_EL1[31] is RES0 but should be made stateful, since it allows programing of CPACR.ASEDIS. Therefore the masking of CPACR_EL1 is removed. Change-Id: If1fa3fa1e06bc38495b8afce2c635f3ddf76ce32 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10046 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-18arch-arm: Mask out unsupported trapped exception handling bitsChuan Zhu
Floating-point trapped exception handlings are not currently supported in gem5, therefore the corresponding bits are RAZ/WI in FCPR. Change-Id: Ica43af62d5f3bbc095e8dd872f0bd365231a5b5f Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10045 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-18arch-arm: Fix FPEXC32_EL2 to FPEXC mappingChuan Zhu
The mapping between MISCREG_FPEXC32_EL2 and MISCREG_FPEXC was missing, this patch adds the mapping. Change-Id: I2e7fa0456b73662ff9f950deb5c7e648a1bdd9ca Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10043 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-18arch-arm: Adding MiscReg Priv (EL1) global flagGiacomo Travaglini
This patch introduces a single global flag for setting RW access permission at EL1 level, in either secure and non-secure mode. Change-Id: I35df66a73349044ca996b5c04c5a2476f3a7abdf Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10042 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-18arch-arm: Correct masking of cp10 and cp11 in CPACRChuan Zhu
This patch fixes the masking of cp10 and cp11 in CPACR according to NSACR.cp10 / NSACR.cp11 by adding the condition "in Non-secure state, if EL3 is implemented and is using AArch32...", which is specified in ARM ARM. Change-Id: Id00e7bf04d6a985e27dbf1028677da0746b79924 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10044 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-18arch-arm: Using explicit invalidation in TLBGiacomo Travaglini
When setting TLB related MiscRegs, using explicit TLB regs invalidation rather than implicit switch-case fallthrough Change-Id: Ia1a7358b6d54dda3811be1c5ce5d676f8c518c4d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10041 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-18mem-cache: Revamp multiple size tracking for FALRU cachesNikos Nikoleris
This change fixes a few bugs and refactors the mechanism by which caches that use the FALRU tags can output statistics for multiple cache sizes ranging from the minimum cache of interest up to the actual configured cache size. Change-Id: Ibea029cf275a8c068c26eceeb06c761fc53aede2 Reviewed-on: https://gem5-review.googlesource.com/9826 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-18dev, arm: Cleanup Pl050 interrupt handlingAndreas Sandberg
Add support for TX interrupts and cleanup existing RX interrupt handling. Change-Id: If2e5b0c0cc6fbeb2dce09e7e9d935647516b2c47 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9769
2018-04-17gpu-compute: fix bad asserts in gpu tlb and cu tlb portTony Gutierrez
change 2a15bfd79ced20a6d4cbf0a0a4c2fbb1444b9a44 introduced a few bugs in the tlb of the cu. asserts in the gpu tlb and cu expected the page table lookup() function to return a bool, and this value was used directly in the gpu tlb's assert and it was kept in the gpu tlb entry, where later the cu would assert that it is true. this change fixes the issue by checking the validity of the pte pointer returned by lookup() in order to set the validity of the tlb entry itself. Change-Id: Ief1f205db65f1911fd132acd314e4407c5e3ffdf Reviewed-on: https://gem5-review.googlesource.com/10001 Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-04-17mem-ruby: enable DPRINTFN calls in slicc for temporary debug printingJohn Alsop
Change-Id: Ib92f8bb4ab7b61ebc96b935cb8abc42cf5ec6ac8 Reviewed-on: https://gem5-review.googlesource.com/9921 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-04-17arch-arm: Fix secure MiscReg access when EL3 is not AArch32Giacomo Travaglini
When EL3 is not implemented or it is running on AArch64, Secure banking does not apply and there is only one flatten register version. In this scenario gem5 is using the _NS (Non-secure) version as a default backing storage location: secure mode software must be able to access the non-secure register. Change-Id: I5086e6228a5cba4d18c632543a2bcf80ffb069a8 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9941 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-17ps2: Unify constant namesAndreas Sandberg
Move ps2.hh to dev/ps2/types.hh and update the device models to consistently use well-known constants from this header. Change-Id: Iadfdc774495957beb82f3d341107b1e9232ffd4c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9770 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-04-17dev, arm: Use the PS/2 framework in the Pl050 modelAndreas Sandberg
The Pl050 KMI model currently has its own keyboard and mouse models. Use the generic PS/2 interface instead. Change-Id: I6523d26f8e38bcc8ba399d4d1a131723645d36c7 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9767 Reviewed-by: Gabe Black <gabeblack@google.com>
2018-04-17ps2: Add proper touchscreen command handlingAndreas Sandberg
The touchscreen model used ad-hoc mechanisms to enable/disable the device. Use standard PS/2 commands to activate/deactivate the device. Add proper TouchKit command handling. Change-Id: I0c5a2e2b47639f36ab3ee07e3e559f11afa54b9d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9768 Reviewed-by: Gabe Black <gabeblack@google.com>
2018-04-17ps2: Implement the keyboard reset commandAndreas Sandberg
Linux tries to reset the PS/2 keyboard at boot. Change-Id: I727fbf6138b654885d82d85be9d964ee3d3365ef Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9766 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-04-17ps2: Unify device data bufferingAndreas Sandberg
All PS/2 device currently implement various ad-hoc mechanisms to handle multi-byte commands. This is error-prone and makes it hard to implement new devices. Create a buffering mechanism in the base class to avoid this. Change-Id: If5638b0ab68decea8de7631ecead0a9ebad1547b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9765 Reviewed-by: Gabe Black <gabeblack@google.com>
2018-04-17ps2: Add a simple touchscreen modelAndreas Sandberg
Add a touchscreen model that is compatible with Linux's TouchKit driver. This model is based on the model in the Arm PL050 KMI model. Change-Id: Id4d88a21a26bb42c455e4d778cd89875f650ac57 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9764 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-04-17ps2: Add VNC support to the keyboard modelAndreas Sandberg
Add support for keyboard input from the VNC server in the PS/2 keyboard model. The introduced code is based on the functionality in the Arm PL050 KMI model. Change-Id: If04a9713e5a15e2149d1a7471b999e3060d8ee7d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9763 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-04-17ps2: Factor out PS/2 devices into their own subsystemAndreas Sandberg
PS/2 devices are currently emulated both in the i8042 model and the Arm KMI model. This is undesirable since it leads to code duplication. This change introduces a common PS/2 device interface and factor out the x86 keyboard and mouse model. A subsequent commit will implement support for this interface in the Arm KMI model. Change-Id: I440e83517fd9dce362fdc1676db477cc6eee5211 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9762 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-04-17mem: Add a helper function to get a word of variable lengthAndreas Sandberg
There are many devices that need to handle reads/writes of different word sizes. A common pattern is a switch statement that check for the size of a packet and then calls the corresponding Packet::(get|set)<uintXX_t> methods. Simplify this by implementing Packet::(get|set)UintX helper functions. The getter reads a word of the size specified in the packet and the specified endianness. The word is then zero-extended to 64 bits. Conversely, the setter truncates the word down to the size required in the packet and then byte-swaps it to the desired endianness. Change-Id: I2f0c27fe3903abf3859bea13b07c7f5f0fb0809f Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9761 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-13ruby,gpu-compute: bugfix for GPU_VIPER* protocolsBrandon Potter
12db50c895 changed how directory mapping works, but it seems to have broken the VIPER variants of the GPU protocols. The fix involves declaring the function in the related '.sm' files. Change-Id: I116980d42a4aa648369058b529c9f8d9693eb894 Reviewed-on: https://gem5-review.googlesource.com/8521 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-04-13ruby: bugfix for MESI_Three_Level protocolBrandon Potter
Since a3177645, the MESI_Three_Level protocol does not build. This changeset addresses the problem by adding the L0Cache machine type to the static machine type declaration in Ruby's export file. Change-Id: I6327547fcb34595619caeb73932c0032f5f65c9f Reviewed-on: https://gem5-review.googlesource.com/8383 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-04-13mem-ruby: fix more style issues in AMD licensesTony Gutierrez
Change-Id: I6585c5664d966989991f61303548aed634cf298a Reviewed-on: https://gem5-review.googlesource.com/9841 Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-04-13mem-cache: Add MoveToTail to FALRUDaniel R. Carvalho
FALRU was missing MoveToTail functionality within its invalidate function, and MoveToHead was doing unnecessary passes when the moved block was the head already. Besides, added some comments to make the code understandable. Change-Id: I2430d82b5d53c88b102a62610ea38b46d6e03a55 Reviewed-on: https://gem5-review.googlesource.com/9541 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-12configs, mem-ruby: fix issues with style in AMD licenseTony Gutierrez
fixes line length and white space issues. Change-Id: Ia04a91ec68cae2bcdabeb93bb1a0f74e8e5486c3 Reviewed-on: https://gem5-review.googlesource.com/9801 Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com> Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
2018-04-10arch-arm: Fix mrc,mcr to cop14 disassembleGiacomo Travaglini
This patch fixes the disassemble for AArch32 mcr/mrc p14 instructions. Change-Id: If5d7c2d7c726f040ae20053bf1d70f4405b34d0e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9681 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-10dev: arm: SetScaling commands don't send parameter bytes.Gabe Black
These are single byte commands which change the mode of the mouse. They don't take any additional parameters like the SetRate or SetResolution. Change-Id: I29194916cfed5d3f4893947ef6d6cc636aee2419 Reviewed-on: https://gem5-review.googlesource.com/9701 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-06arch: alpha: Fix an 8 year old bug from the transition to pc objects.Gabe Black
When we transitioned from having PCs and nextPCs stored as individual items in the ThreadContext and went to having PC objects with abstracted components (micro PCs, delay slots, variable instruction lengths, etc.), a small mistake was made when translating the alpha StackTrace code. Change-Id: Ib5dd65c53a26920e66899f421902607efd139e71 Reviewed-on: https://gem5-review.googlesource.com/9702 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-04-06util,arch-arm: Update gen_arm_fs_files.py to use new kernel reposPau Cabre
Now it is using the kernels on https://gem5.googlesource.com/arm Change-Id: I765f2b8ee48cfd7175e5b17a65db3bf612570c68 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/9481 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-06arch-arm: Add support for Tarmac trace generationGiacomo Travaglini
This patch introduces the TarmacTracer: an instruction tracer which allows to dump a gem5 execution trace in Tarmac format [1]. The new tracer is supporting either Tarmac and TarmacV8 format specifications. Not every traceable information has been implemented: Implemented Trace Type: Instruction Trace Register Trace Processor Memory Access Trace Unimplemented Trace Type: Program Flow Trace Event Trace Memory Bus Trace [1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format Change-Id: I8799d8e5852e868673f728971db3fe8c63961f5e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9382 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-06arch-arm: Add support for Tarmac trace-based simulationGiacomo Travaglini
A new InstTracer (TarmacParser) has been implemented. This tracer is parsing a pre-existing Tarmac trace file [1] while gem5 is running; it is comparing execution data together with trace data and it is dumping differences. This allows to use Tarmac format as a glue between heterogeneous simuators speaking the same Tarmac language. Kudos to Giacomo Gabrielli for writing the original tracer. [1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format Change-Id: I9b92204a149813166166adba4a7c61a248bdcac3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9381 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-06arch-arm: Fix AArch32 branch instructions disassembleGiacomo Travaglini
This patch adds the generateDisassembly method for BranchReg, BranchImm and BranchRegReg Base classes used by AArch32 branch instructions. Change-Id: I6de015cc213335556d5187df3d4fcd765876262c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9503 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-06arch-arm: Fix secure write of SCTLR when EL3 is AArch64Giacomo Travaglini
MiscRegisters are not banked between secure and non-secure mode if EL3 is not implemented or if EL3 is using AArch64 (highestELIs64). In this scenario a unique register is used and it is mapped to the NS version (see snsBankedIndex implementation), so that a secure world read/write should access the non secure storage. Change-Id: Ica4182e3cdf4021d2bd1db23e477ce2bbf055926 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9502 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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