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2008-02-26Update make release, README, and RELEASE_NOTES for b5Ali Saidi
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2008-02-26Bus: Update the stats for the recent bus fix.Gabe Black
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2008-02-26Bus: Fix the bus timing to be more realistic.Gabe Black
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2008-02-22add instruction count fast forwaing and max instruction optionsVilas Sridharan
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2008-02-19Added ARM_SE as a build option.Stephen Hines
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2008-02-16Update stats for new writeback behavior.Steve Reinhardt
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2008-02-16Make L2+ caches allocate new block for writeback missesSteve Reinhardt
instead of forwarding down the line. --HG-- extra : convert_revision : b0d6e7862c92ea7a2d21f817d30398735e7bb8ba
2008-02-16Update stats for some unknown minor x86 changesSteve Reinhardt
(assuming someone just forgot to do this... tsk tsk). --HG-- extra : convert_revision : 303d7bbf5e2c892d5f4498a9de2e2b82496ccd0e
2008-02-14CPU: move the PC Events code to a place where the code won't be executed ↵Ali Saidi
multiple times if an instruction faults. --HG-- extra : convert_revision : 19c8e46a4eea206517be7ed4131ab9df0fe00e68
2008-02-14Configs: Change Simulation.py to return a subclass of the CPU models rather ↵Ali Saidi
than the original class. Without this changes elsewhere in the config script (e.g. the DriveSys frequency can change the TestSys frequency. --HG-- extra : convert_revision : f972207c616590a60a6e103daa5de469cf124b44
2008-02-11Update copyright datesAli Saidi
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2008-02-11Automated merge with file:/home/stever/hg/m5-origSteve Reinhardt
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2008-02-11EXTRAS now points to src instead of needing 'src' subdir.Steve Reinhardt
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2008-02-11Wait to set BUILD_DIR until *after* env is copied.Steve Reinhardt
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2008-02-10Bus: Only update port cache when there is an item to update it with.Nicolas Zea
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2008-02-10IGbE: Fix a couple of bugs.Ali Saidi
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2008-02-10Fix #include lines for renamed cache files.Steve Reinhardt
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2008-02-10Rename cache files for brevity and consistency with rest of tree.Steve Reinhardt
--HG-- rename : src/mem/cache/base_cache.cc => src/mem/cache/base.cc rename : src/mem/cache/base_cache.hh => src/mem/cache/base.hh rename : src/mem/cache/cache_blk.cc => src/mem/cache/blk.cc rename : src/mem/cache/cache_blk.hh => src/mem/cache/blk.hh rename : src/mem/cache/cache_builder.cc => src/mem/cache/builder.cc rename : src/mem/cache/miss/mshr.cc => src/mem/cache/mshr.cc rename : src/mem/cache/miss/mshr.hh => src/mem/cache/mshr.hh rename : src/mem/cache/miss/mshr_queue.cc => src/mem/cache/mshr_queue.cc rename : src/mem/cache/miss/mshr_queue.hh => src/mem/cache/mshr_queue.hh rename : src/mem/cache/prefetch/base_prefetcher.cc => src/mem/cache/prefetch/base.cc rename : src/mem/cache/prefetch/base_prefetcher.hh => src/mem/cache/prefetch/base.hh rename : src/mem/cache/prefetch/ghb_prefetcher.cc => src/mem/cache/prefetch/ghb.cc rename : src/mem/cache/prefetch/ghb_prefetcher.hh => src/mem/cache/prefetch/ghb.hh rename : src/mem/cache/prefetch/stride_prefetcher.cc => src/mem/cache/prefetch/stride.cc rename : src/mem/cache/prefetch/stride_prefetcher.hh => src/mem/cache/prefetch/stride.hh rename : src/mem/cache/prefetch/tagged_prefetcher.cc => src/mem/cache/prefetch/tagged.cc rename : src/mem/cache/prefetch/tagged_prefetcher.hh => src/mem/cache/prefetch/tagged.hh rename : src/mem/cache/tags/base_tags.cc => src/mem/cache/tags/base.cc rename : src/mem/cache/tags/base_tags.hh => src/mem/cache/tags/base.hh rename : src/mem/cache/tags/Repl.py => src/mem/cache/tags/iic_repl/Repl.py rename : src/mem/cache/tags/repl/gen.cc => src/mem/cache/tags/iic_repl/gen.cc rename : src/mem/cache/tags/repl/gen.hh => src/mem/cache/tags/iic_repl/gen.hh rename : src/mem/cache/tags/repl/repl.hh => src/mem/cache/tags/iic_repl/repl.hh extra : convert_revision : ff7a35cc155a8d80317563c45cebe405984eac62
2008-02-06Make the Event::description() a const functionStephen Hines
--HG-- extra : convert_revision : c7768d54d3f78685e93920069f5485083ca989c0
2008-02-05Add base ARM code to M5Stephen Hines
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2008-02-05Cleaned up os.path imports a bit.Steve Reinhardt
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2008-02-05Make EXTRAS work for SConsopts too.Steve Reinhardt
Requires pushing source files down into 'src' subdir relative to directory listed in EXTRAS. --HG-- extra : convert_revision : ca04adc3e24c60bd3e7b63ca5770b31333d76729
2008-01-23X86: Put an SMBios/DMI table in memory.Gabe Black
This is basically just the header right now, but there's an untested mechanism in place to fill out the table and make sure everything is updated correctly. --HG-- extra : convert_revision : c1610c0dfa211b7e0d091a04133695d84f500a1c
2008-01-23X86: Optomize the bit scanning instruction microassembly a little. More can ↵Gabe Black
be done. --HG-- extra : convert_revision : 3cf6e972f0e41e3529a633ecbb31289e1bd17f0f
2008-01-22X86: Implement and attach the BSR and BSF instructions.Gabe Black
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2008-01-21X86: Fill out group17 in the decoder.Gabe Black
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2008-01-21X86: Use the existing boot_osflags instead of duplicating it.Gabe Black
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2008-01-16Update long o3 regressions for o3 change in previous changesetAli Saidi
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2008-01-15Update O3 ref outputs: very minor stats change due to previous cset.Steve Reinhardt
(from Steve on behalf of m5test). --HG-- extra : convert_revision : 696efdaa3dd7680dfc9c797a6a46a5053238c7d2
2008-01-14The reason is that the event is supposed to put the instructions ready to ↵Ke Meng
execute for next cycle. And the FUCompletion event has a lower priority than CPU tick event. It is called after the iew->tick() for current cycle has already been executed and the issueToExecuteQueue has already advanced this time. And assume the issueToExecuteLatency is 1, to catch up, the increasement should be made at access(-1) instead of access(0). Otherwise I found it could increase the actual op_latency of the instructions to execute by 1 cycle and potentially put the simulated CPU into a permanent idle state. Signed-off by: Ali Saidi <saidi@eecs.umich.edu> --HG-- extra : convert_revision : dafc16814383e8e8f8320845edf6ab2bcfed1e1d
2008-01-12X86: Redo the bit test instructions.Gabe Black
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2008-01-12X86: Fix the wrmsr instruction.Gabe Black
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2008-01-12X86: Make the effective segment base shadow the regular one, not the selector.Gabe Black
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2008-01-12X86: Make the IO ports work using extra physical address lines. Add a serial ↵Gabe Black
port. --HG-- extra : convert_revision : a14cb4fc9afedfc0ff58b11a7f8fb5516d462cc6
2008-01-12X86: Fix the general IO instructions dataSize.Gabe Black
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2008-01-06Temporary fix for ll/sc bug see flyspray task for more info:Geoffrey Blake
http://www.m5sim.org/flyspray/task/197 Signed-off by: Ali Saidi <saidi@eecs.umich.edu> --HG-- extra : convert_revision : cdeece7e3163de9abf2c6c7435f1bc93570fab81
2008-01-02Very minor memtest regression stats changes from recent coherence bug fixes.Steve Reinhardt
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2008-01-02Add ReadRespWithInvalidate to handle multi-level coherence situationSteve Reinhardt
where we defer a response to a read from a far-away cache A, then later defer a ReadExcl from a cache B on the same bus as us. We'll assert MemInhibit in both cases, but in the latter case MemInhibit will keep the invalidation from reaching cache A. This special response tells cache A that it gets the block to satisfy its read, but must immediately invalidate it. --HG-- extra : convert_revision : f85c8b47bb30232da37ac861b50a6539dc81161b
2008-01-02Mark cache-to-cache MSHRs as downstreamPending when necessary.Steve Reinhardt
Don't mark upstream MSHR as pending if downstream MSHR is already in service. --HG-- extra : convert_revision : e1c135ff00217291db58ce8a06ccde34c403d37f
2008-01-02Don't DPRINTF in the middle of a PrintReq.Steve Reinhardt
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2008-01-02Bug fix: functional cache port now needs otherPort set.Steve Reinhardt
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2008-01-02Additional comments and helper functions for PrintReq.Steve Reinhardt
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2008-01-02Add functional PrintReq command for memory-system debugging.Steve Reinhardt
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2008-01-02Fix formatting and comments in cache_impl.hhSteve Reinhardt
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2008-01-01SPARC: Fix a bug where the TLB would match against the wrong entries.Gabe Black
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2007-12-18Checkpointing: Fix a bug in the simulation script when restoring without ↵Ali Saidi
standard switch and change some ifs to work with the default port since every port is now connected to something. --HG-- extra : convert_revision : 72507cf13e58465291b0dce6322e853bee5a2b89
2007-12-16CPU: Update where the simple cpus read their cpu id from the thread context ↵Ali Saidi
to init() to make sure they read the right value. This fixes a bug with multi-processor full-system configurations. --HG-- extra : convert_revision : 4f2801967a271b43817d88e147c2f80c4480b2c3
2007-12-11Fix minor bug in util/style.pySteve Reinhardt
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2007-12-03X86: Update the parser reference output which has mysteriously changed again?Gabe Black
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2007-12-03X86: Please excuse my dear Aunt Sally. (precedence bug)Gabe Black
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