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2017-07-20sim: Prevent segfault in the wakeCpu m5op if id is invalidJose Marinho
Change-Id: I86229cedb206e10326cdee3f09a5c871e49c8d48 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3965
2017-07-19cpu: Add missing rename of vector registers in the O3 CPURekai Gonzalez-Alberquilla
The introduction of a new vector register class broke rename in the O3 CPU due to an unhandled register class in DefaultRename<Impl>::renameSrcRegs(). This patch fixes adds the necessary handling to avoid a panic when the vector register file is used. Change-Id: Ie380ab35ec4a151db15402f25b25b58931ee0581 Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4140 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-17cpu,o3: Fixed checkpointing bug occuring in the o3 CPUAnouk Van Laer
Checkpointing a system with out-of-order CPUs might get stuck if one of the CPUs has been put to sleep. The quiesce instruction cannot get drained hence checkpointing never finishes. This commit resolves that by activating all suspended thread contexts when draining the system. Change-Id: I817ab1672b4ead777bd8e12a0445829481c46fdc Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3970 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-17tests: Don't treat new stats as a cause for failuresAndreas Sandberg
We currently fail the stat diff stage of tests if there are new stats. This is usually undesirable since this would require any change that adds a stat to also update the regressions. Change-Id: Ieadebac6fd17534e1b49b6b9a1d56f037a423325 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3962 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-17sim, x86: Make clone a virtual functionSean Wilson
This fixes the function call to clone in syscall_emul.hh where the x86 version should be called before the base implementation of clone. Change-Id: Iccd2f680ff6e3a5536037d688a80ab3f236bbd98 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3902 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-17x86: Add stats to X86 TLBSwapnil Haria
Change-Id: Iebf7d245de66eebc8d4c59e62e52adf6cf51e1e4 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3980 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-17riscv: Define register index constants using literalsAlec Roelke
To make it clearer what the register indices are for the semantically meaningful registers defined by src/arch/riscv/registers.hh, the constants that were defined using other constants were changed to use the literal values of those constants. This also removes the need to use the M5_VAR_USED attribute. Change-Id: I7cccbe45d3d820deb5149a5925415735f6ae2e61 Reviewed-on: https://gem5-review.googlesource.com/4080 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-07-14riscv: Disambiguate between the C and C++ versions of isnan and isinf.Gabe Black
When both the C and C++ versions are visible, the compiler will complain that it doesn't know which one to use. By specifying the std namespace, it will know to use the C++ version. Change-Id: Ie1bbe1d95eadbad9644b4915c21f924d7d5c0b22 Reviewed-on: https://gem5-review.googlesource.com/4060 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-07-14tests: Upate RISC-V binaries and resultsAlec Roelke
This patch updates the binaries and results for hello and insttest regressions using the compressed extension. Change-Id: I3d8f2248f490521d3e0dc05c48735cab82b1b04e Reviewed-on: https://gem5-review.googlesource.com/4042 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-14riscv: Fix bugs with RISC-V decoder and detailed CPUsAlec Roelke
This patch fixes some bugs that were missed with the changes to the decoder that enabled compatibility with compressed instructions. In order to accommodate speculation with variable instruction widths, a few assertions in decoder had to be changed to returning faults as the specification describes should normally happen. The rest of these assertions will be changed in a later patch. [Remove commented-out debugging line and add clarifying comment to registerName in utility.hh.] Change-Id: I3f333008430d4a905cb59547a3513f5149b43b95 Reviewed-on: https://gem5-review.googlesource.com/4041 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-07-14riscv: Add unused attribute to some registers.hh constantsAlec Roelke
Three of the constants defined in arch/riscv/registers.hh (ReturnValueReg, SyscallNumReg, and SyscallPseudoReturnReg) may cause the compiler to warn that they are unused, which results in an error. This patch adds M5_VAR_USED attributes to them to stop this. Change-Id: Ie6389a55e8ffb3d003a47d02e76bdf9fb5219457 Reviewed-on: https://gem5-review.googlesource.com/4040 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-07-13arch-arm: fix ldm of pc interswitching branchGedare Bloom
The LDM instruction that loads to the PC causes a branch to the instruction. In ARMv5T+ the branch can interswitch Thumb and ARM modes. The interswitch is broken prior to this commit, with LDM to the PC ignoring the switch. Change-Id: I6aad073206743f3435c9923e3e2218bfe32c7e05 Reviewed-on: https://gem5-review.googlesource.com/3520 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-12ruby: Refactor some Event subclasses to lambdasSean Wilson
Change-Id: I9f47a20a869553515a759d9a29c05f6ce4b42d64 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3930 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-07-12arm: Refactor some Event subclasses to lambdasSean Wilson
Change-Id: Ic59add8afee1d49633634272d9687a4b1558537e Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3929 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-12dev: Refactor some Event subclasses to lambdasSean Wilson
Change-Id: I965d31ff8ad1658b03a902bf4244d7d0977b0466 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3928 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-12net: Refactor some Event subclasses to lambdasSean Wilson
Change-Id: I0e23f1529b26c36d749bf5211ee8623744d0b10f Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3927 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-12testers: Refactor some Event subclasses to lambdasSean Wilson
Change-Id: I897b6162a827216b7bad74d955c0e50e06a5a3ec Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3926 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-07-12kvm, mem: Refactor some Event subclasses into lambdasSean Wilson
Change-Id: Ifafdcf4692d58a17f90e66ff8de8fa3e146c34bb Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3924 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-12cpu: Refactor some Event subclasses to lambdasSean Wilson
Change-Id: If765c6100d67556f157e4e61aa33c2b7eeb8d2f0 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3923 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-12gpu-compute: Refactor some Event subclasses to lambdasSean Wilson
Change-Id: Ic1332b8e8ba0afacbe591c80f4d06afbf5f04bd9 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3922 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2017-07-12sim, gdb: Refactor some Event subclasses into lambdasSean Wilson
Change-Id: If3e4329204f27eda96b50ec6ac279ebc6ef23d99 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3921 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-12mips, x86: Refactor some Event subclasses into lambdasSean Wilson
Change-Id: I09570e569efe55f5502bc201e03456738999e714 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3920 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-07-12util,arch-arm: Added python script to generate ARM FS binariesPau Cabre
This python script builds the bootloaders, kernels and DTBs for the VExpress_GEM5_V1 (aarch32/aarch64), VExpress_EMM and VExpress_EMM64 platforms (it checkouts some linux kernel repositories when needed). This is the result of this e-mail thread in gem5-dev mailing list: http://www.mail-archive.com/gem5-dev@gem5.org/msg22406.html Change-Id: Ida8f9b974f7188f48be8f84f14828a1973d6d256 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/3945 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-12cpu, sim: Add param to force CPUs to wait for GDBJose Marinho
By setting the BaseCPU parameter wait_for_dbg_connection, the GDB server blocks during initialisation waiting for the remote debugger to connect before starting the simulated CPU. Change-Id: I4d62c68ce9adf69344bccbb44f66e30b33715a1c [ Update info message to include remote GDB port, rename param. ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3963 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
2017-07-11arch-riscv,tests: Add insttests for RV64CAlec Roelke
This patch adds instruction tests for the RV64C extension implementation. It also updates existing executables for the latest riscv-tools now that they are compatible. [Update for changes to parents.] Change-Id: Id4cfd966a8cae39b0d728b02849622fd00ee7e0e Reviewed-on: https://gem5-review.googlesource.com/3862 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-07-11arch-riscv: Add support for compressed extension RV64CAlec Roelke
This patch adds compatibility with the 64-bit compressed extension to the RISC-V ISA, RV64C. Current versions of the toolchain may use compressed instructions in glibc by default, which can only be overridden by recompiling the entire toolchain (simply adding "-march=rv64g" or "-march=rv64imafd" when compiling a binary is not sufficient to use uncompressed instructions in glibc functions in the binary). [Update diassembly generation for new RegId type.] [Rebase onto master.] Change-Id: Ifd5a5ea746704ce7e1b111442c3eb84c509a98b4 Reviewed-on: https://gem5-review.googlesource.com/3860 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-07-11arch-riscv: Restructure ISA descriptionAlec Roelke
This patch restructures the RISC-V ISA description to use fewer classes and improve its ability to be extended with nonstandard extensions in the future. It also cleans up the disassembly for some of the CSR and system instructions by removing source and destination registers for instructions that don't have any. [Fix class UImmOp to have an "imm" member rather than "uimm".] [Update disassembly generation for new RegId class.] Change-Id: Iec1c782020126e5e8e73460b84e31c7b5a5971d9 Reviewed-on: https://gem5-review.googlesource.com/3800 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-07-10dev-arm: Add ID registers to the GIC modelJose Marinho
Implement GICD_IIDR, GICC_IIDR, GICD_PIDR0, GICD_PIDR1, GICD_PIDR2, and GICD_PIDR3. Change-Id: I4f6b5a6303907226e7d8e2f677543b3868c02e7b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3961
2017-07-10arch-arm: Support PMU evens in the 0x4000-0x4040 rangeJose Marinho
ARMv8.1 added a second architected event range, 0x4000-0x4040. Events in this range are discovered using the high word of PMCEID{0,1}_EL0 Change-Id: I4cd01264230e5da4c841268a7cf3e6bd307c7180 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3960
2017-07-10dev-arm: Don't unconditionally overwrite bootloader paramsJose Marinho
The bootloader arguments were previously defaulting to a predetermined value even if initialized elsewhere in the platform config script. This commit fixes this issue by not calling the default initialization routine if the bootloader is already defined. Change-Id: Id80af4762b52dc036da29430b2795bb30970a349 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3967
2017-07-10dev: Fix OnIdle test in DmaReadFifoRohit Kurup
OnIdle() is never called since DMA active check is completely opposite to what it should be. old active status should be 'true' and new active status should be false for OnIdle to be called Change-Id: I94eca50edbe96113190837c7f6e50a0d061158a6 Reported-by: Rohit Kurup <rohit.kurup@arm.com> Signed-off-by: Rohit Kurup <rohit.kurup@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3966 Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
2017-07-10dev: Fix address type promotion issues in VirtIO devicesSascha Bischoff
With the change we explicitly update the types for the VirtIO bit masks to be Addr (uint64_t). By changing this, we ensure type promotion where it is needed. Therefore, this fixes issues where, in certain situations, address calculations were performed in 32-bits, resulting in overflows. Change-Id: I5c5c3f9a3f94e806812282da01268e18ae0d2d39 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3968
2017-07-10sim: Fix clashing stat names in TickedObject and TickedJose Marinho
Change tickCycles numCycles stat name to totalTickCycles os as not to clash with the name of the tickCycles stat of the same class. Declared the params passed to the TickedObject constructer as const. Call ClockedObject::regStats() from the TickedObject::regStats to ensure the correct initialization of the base class (ClockedObject) stats Change-Id: I6cf5bbe10fa27f2ad0e31d9f70ec3be47fe41455 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3964 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-07kvm, arm: don't create interrupt events while saving GIC stateCurtis Dunham
If an interrupt was pending according to Kvm state during a drain, the Pl390 model would create an interrupt event that could not be serviced, preventing the system from draining. The proper behavior is for the Pl390 not actively being used for simulation to just skip the GIC state machine that delivers interrupts. Change-Id: Icb37e7e992f1fb441a9b3a26daa1bb5a6fe19228 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3661 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-07kvm, arm: Don't forward IRQ/FIQ when using the kernel's GICAndreas Sandberg
The BaseArmKvmCPU is responsible for forwarding the IRQ and FIQ signals from gem5's simulated GIC to KVM. However, these signals shouldn't be used when the in-kernel GIC emulator is used. Instead of delivering the interrupts to the guest, we should just ignore them since any such pending interrupts are likely to be an artifact of CPU switching or incorrect draining. Change-Id: I083b72639384272157f92f44a6606bdf0be7413c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3660
2017-07-05arch: ISA parser additions of vector registersRekai Gonzalez-Alberquilla
Reiley's update :) of the isa parser definitions. My addition of the vector element operand concept for the ISA parser. Nathanael's modification creating a hierarchy between vector registers and its constituencies to the isa parser. Some fixes/updates on top to consider instructions as vectors instead of floating when they use the VectorRF. Some counters added to all the models to keep faithful counts. Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2706 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-05cpu: Added interface for vector reg fileRekai Gonzalez-Alberquilla
This patch adds some more functionality to the cpu model and the arch to interface with the vector register file. This change consists mainly of augmenting ThreadContexts and ExecContexts with calls to get/set full vectors, underlying microarchitectural elements or lanes. Those are meant to interface with the vector register file. All classes that implement this interface also get an appropriate implementation. This requires implementing the vector register file for the different models using the VecRegContainer class. This change set also updates the Result abstraction to contemplate the possibility of having a vector as result. The changes also affect how the remote_gdb connection works. There are some (nasty) side effects, such as the need to define dummy numPhysVecRegs parameter values for architectures that do not implement vector extensions. Nathanael Premillieu's work with an increasing number of fixes and improvements of mine. Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues and CC reg free list initialisation ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2705
2017-07-05arch: added generic vector registerRekai Gonzalez-Alberquilla
This commit adds a new generic vector register to have a cleaner implementation of SIMD ISAs. Nathanael's idea, Rekai's implementation. Change-Id: I60b250bba6423153b7e04d2e6988d517a70a3e6b Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2704 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-05cpu: Result refactoringRekai Gonzalez-Alberquilla
The Result union used to collect the result of an instruction is now a class of its own, with its constructor, and explicit casting methods for cleanliness. This is also a stepping stone to have vector registers, and instructions that produce a vector register as output. Change-Id: I6f40c11cb5e835d8b11f7804a4e967aff18025b9 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2703 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-05cpu: Simplify the rename interface and use RegIdRekai Gonzalez-Alberquilla
With the hierarchical RegId there are a lot of functions that are redundant now. The idea behind the simplification is that instead of having the regId, telling which kind of register read/write/rename/lookup/etc. and then the function panic_if'ing if the regId is not of the appropriate type, we provide an interface that decides what kind of register to read depending on the register type of the given regId. Change-Id: I7d52e9e21fc01205ae365d86921a4ceb67a57178 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2702
2017-07-05cpu: Physical register structural + flat indexingNathanael Premillieu
Mimic the changes done on the architectural register indexes on the physical register indexes. This is specific to the O3 model. The structure, called PhysRegId, contains a register class, a register index and a flat register index. The flat register index is kept because it is useful in some cases where the type of register is not important (dependency graph and scoreboard for example). Instead of directly using the structure, most of the code is working with a const PhysRegId* (typedef to PhysRegIdPtr). The actual PhysRegId objects are stored in the regFile. Change-Id: Ic879a3cc608aa2f34e2168280faac1846de77667 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2701 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-05arch, cpu: Architectural Register structural indexingNathanael Premillieu
Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700
2017-07-05arm,kvm: update CP15 timer model when exiting KvmCurtis Dunham
The ARM MiscRegs implementation has two interfaces: 'normal' and 'no effect'. The latter acts as a way to access the backing store without architectural 'effects'. For instance, a normal write to a timer compare value would call into the timer model to emulate the device. The 'no effect' interface, however, would just write the value into the register backing store and do nothing else. For Kvm execution, a delicate balance must be struck for the timer device specifically. We need the code in the model to be run, because it contains state other than the register backing store that must stay in sync. On the other hand, we don't necessarily want the timer model to schedule gem5 events when this happens. In this commit, we ensure that we use the 'effectful' MiscReg interface when copying the CP15 timer registers from Kvm back into gem5. The prior commit makes sure that this doesn't generate unnecessary timer events or interrupts. Change-Id: Id414c2965bd07fc21ac95e3d581ccc9f55cef9f9 Reviewed-on: https://gem5-review.googlesource.com/3543 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-05dev,arm: add Kvm mode of operation for CP15 timerCurtis Dunham
The timer device exposed via the ARM ISA, also known as the "CP15 timer" due to its legacy coprocessor encodings, is implemented by the GenericTimerISA class. During Kvm execution, however, this functionality is directly emulated by the hardware. This commit subclasses the GenericTimer, which is (solely) used by GenericTimerISA, to facilitate Kvm in much the same way as the prior GIC changes: the gem5 model is used as the backing store for state, so checkpointing and CPU switching work correctly, but isn't used during Kvm execution. The added indirection prevents the timer device from creating events when we're just updating its state, but not actually using it for simulation. Change-Id: I427540d11ccf049c334afe318f575146aa888672 Reviewed-on: https://gem5-review.googlesource.com/3542 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-05dev,arm: remove and recreate timer events around drainsCurtis Dunham
Having timer events stored in checkpoints complicates Kvm execution. We change the timer behavior so that it always deschedules any pending events on a drain() and recreates them on a drainResume(), thus they will never appear in checkpoints henceforth. This pattern of behavior makes it simpler to handle Kvm execution, where the hardware performs the timer function directly. Change-Id: Ia218868c69350d96e923c640634d492b5c19cd3f Reviewed-on: https://gem5-review.googlesource.com/3541 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-05kvm: move Kvm check from ARM Kvm GIC to SystemCurtis Dunham
The check was nearly completely generic anyway, with the exception of the Kvm CPU type. This will make it easier for other parts of the codebase to do similar checks. Change-Id: Ibfdd3d65e9e6cc3041b53b73adfabee1999283da Reviewed-on: https://gem5-review.googlesource.com/3540 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-04config, arm: Don't import timing models for missing CPUsAndreas Sandberg
When importing the cores.arm package, we currently throw an exception if a timing model can't be imported due to a missing dependency (e.g., the required CPU model wasn't included in the build). This is undesirable since it prevents other, working, timing models from being added to the package. Wrap the import_module call in a try-except block and skip timing models that have missing dependencies. Change-Id: I92bab62c989f433a8a4a7bf59207d9d81b3d19e1 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3946 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-03config: Clean up core timing model discoveryAndreas Sandberg
Instead of hard-coding timing models in CpuConfig.py, use introspection to find them in the cores.arm model package. Change-Id: I6642dc9cbc3f5beeeec748e716c9426c233d51ea Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3944 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-03config: Move core timing models to config/common/coresAndreas Sandberg
Change-Id: I189b6462cc64f7cc6c1b7a6c2af1abb60e1854de Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3943 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-03config: Make ex5_*.py independent of old configsAndreas Sandberg
The ex5_LITTLE and ex5_big configs currently depend on Caches.py and O3_ARM_v7a.py. These aren't actual dependencies since all of the params from the caches and the old O3 model are overridden. This changeset updates the ex5 models to derive from the base SimObjects instead. Change-Id: I999e73bb9cc21ad96865c1bc0dd5973faa48ab61 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3942 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
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