gem5 - gem5

Age	Commit message (Expand)	Author
2012-10-25	stats: Update stats to reflect use of SimpleDRAM	Andreas Hansson
2012-10-25	config: Use SimpleDRAM in full-system, and with o3 and inorder	Andreas Hansson
2012-10-25	config: Use shared cache config for regressions	Andreas Hansson
2012-10-25	arm: Use table walker clock that is inherited from CPU	Andreas Hansson
2012-10-23	stats: Update stats for DMA port send	Andreas Hansson
2012-10-23	dev: Remove zero-time loop in DMA timing send	Andreas Hansson
2012-10-23	stats: Update t1000 stats to match recent changes	Andreas Hansson
2012-10-18	ruby: functional access updates to network test protocol	Nilay Vaish
2012-10-16	regressions: update stats for eio tests	Nilay Vaish
2012-10-15	regressions: update stats due to change to ruby memory system	Nilay Vaish
2012-10-15	ruby: improved support for functional accesses	Nilay Vaish
2012-10-15	memtest: move check on outstanding requests	Nilay Vaish
2012-10-15	ruby: register multiple memory controllers	Nilay Vaish
2012-10-15	ruby: remove AbstractMemOrCache	Nilay Vaish
2012-10-15	ruby: allow function definition in slicc structs	Nilay Vaish
2012-10-15	ruby banked array: do away with event scheduling	Nilay Vaish
2012-10-15	ruby: reset timing after cache warm up	Nilay Vaish
2012-10-15	Mem: Fix incorrect logic in bus blocksize check	Andreas Hansson
2012-10-15	Port: Add protocol-agnostic ports in the port hierarchy	Andreas Hansson
2012-10-15	Mem: Separate the host and guest views of memory backing store	Andreas Hansson
2012-10-15	Checkpoint: Make system serialize call children	Andreas Hansson
2012-10-15	Mem: Use deque instead of list for bus retries	Andreas Hansson
2012-10-15	Fix: Address a few minor issues identified by cppcheck	Andreas Hansson
2012-10-15	Stats: Update stats for cache timings in cycles	Andreas Hansson
2012-10-15	Mem: Use cycles to express cache-related latencies	Andreas Hansson
2012-10-15	Stats: Update memtest stats after setting clock	Andreas Hansson
2012-10-15	Configs: Set the memtest clock to a reasonable value	Andreas Hansson
2012-10-15	Stats: Update stats for new default L1-to-L2 bus clock and width	Andreas Hansson
2012-10-15	Regression: Use CPU clock and 32-byte width for L1-L2 bus	Andreas Hansson
2012-10-15	Stats: Update stats for use of two-level builder	Andreas Hansson
2012-10-15	Regression: Use addTwoLevelCacheHierarchy in configs	Andreas Hansson
2012-10-15	Clock: Inherit the clock from parent by default	Andreas Hansson
2012-10-15	Param: Fix proxy traversal to support chained proxies	Andreas Hansson
2012-10-15	Mem: Use range operations in bus in preparation for striping	Andreas Hansson
2012-10-11	Mem: Determine bus block size during initialisation	Andreas Hansson
2012-10-11	Doxygen: Update the version of the Doxyfile	Andreas Hansson
2012-10-02	Regression Tests: Update statistics	Nilay Vaish
2012-10-02	ruby: makes some members non-static	Nilay Vaish
2012-10-02	ruby: changes to simple network	Nilay Vaish
2012-10-02	ruby: rename template_hack to template	Nilay Vaish
2012-10-02	ruby: remove unused code in protocols	Nilay Vaish
2012-10-02	ruby: remove some unused things in slicc	Nilay Vaish
2012-10-02	ruby: move functional access to ruby system	Nilay Vaish
2012-09-30	MI coherence protocol: add copyright notice	Nilay Vaish
2012-09-28	Configs: SE script fix for Alpha and Ruby simulations	Malek Musleh
2012-09-27	Configs: Fix memtest cache latency to match new parameters	Andreas Hansson
2012-09-27	Configs: Fix memtest.py by moving the system port	Andreas Hansson
2012-09-25	ARM: update stats for bp and squash fixes.	Ali Saidi
2012-09-25	MEM: Put memory system document into doxygen	Djordje Kovacevic
2012-09-25	Cache: add a response latency to the caches	Mrinmoy Ghosh