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2010-08-20MOESI_CMP_token: Fixed dma persistent lockdown bugsBrad Beckmann
2010-08-20memtest: Memtester support for DMABrad Beckmann
This patch adds DMA testing to the Memtester and is inherits many changes from Polina's old tester_dma_extension patch. Since Ruby does not work in atomic mode, the atomic mode options are removed.
2010-08-20ruby: Added ruby_request_type ostream def to libruby.hhBrad Beckmann
2010-08-20slicc: Consolidated the protocol stats printingBrad Beckmann
Created a separate ProfileDumper that consolidates the generated stats for each controller of a certain type.
2010-08-20config: Improve ruby simobject namesBrad Beckmann
This patch attaches ruby objects to the system before the topology is created so that their simobject names read their meaningful variable names instead of their topology name.
2010-08-20config: Added the topology description to m5 config.iniBrad Beckmann
2010-08-20ruby: added token broadcast config params to cmd optionsBrad Beckmann
2010-08-20config: reorganized how ruby specifies command-line optionsBrad Beckmann
2010-08-20ruby: Fixed printout when Sequencer detects a deadlockBrad Beckmann
2010-08-20MESI_CMP_directory: bug fix for old PUTX requestsBrad Beckmann
2010-08-20config: moved python protocol config filesBrad Beckmann
Moved the python protocol config files back to their original location to avoid addToPath calls. --HG-- rename : configs/ruby/protocols/MESI_CMP_directory.py => configs/ruby/MESI_CMP_directory.py rename : configs/ruby/protocols/MI_example.py => configs/ruby/MI_example.py rename : configs/ruby/protocols/MOESI_CMP_directory.py => configs/ruby/MOESI_CMP_directory.py rename : configs/ruby/protocols/MOESI_CMP_token.py => configs/ruby/MOESI_CMP_token.py rename : configs/ruby/protocols/MOESI_hammer.py => configs/ruby/MOESI_hammer.py
2010-08-17misc: add some AMD copyright noticesSteve Reinhardt
Meant to add these with the previous batch of csets.
2010-08-17x86: minor checkpointing bug fixesSteve Reinhardt
2010-08-17sim: revamp unserialization procedureSteve Reinhardt
Replace direct call to unserialize() on each SimObject with a pair of calls for better control over initialization in both ckpt and non-ckpt cases. If restoring from a checkpoint, loadState(ckpt) is called on each SimObject. The default implementation simply calls unserialize() if there is a corresponding checkpoint section, so we get backward compatibility for existing objects. However, objects can override loadState() to get other behaviors, e.g., doing other programmed initializations after unserialize(), or complaining if no checkpoint section is found. (Note that the default warning for a missing checkpoint section is now gone.) If not restoring from a checkpoint, we call the new initState() method on each SimObject instead. This provides a hook for state initializations that are only required when *not* restoring from a checkpoint. Given this new framework, do some cleanup of LiveProcess subclasses and X86System, which were (in some cases) emulating initState() behavior in startup via a local flag or (in other cases) erroneously doing initializations in startup() that clobbered state loaded earlier by unserialize().
2010-08-17sim: fold checkpoint restore code into instantiate()Steve Reinhardt
The separate restoreCheckpoint() call is gone; just pass the checkpoint dir as an optional arg to instantiate(). This change is a precursor to some more extensive reworking of the startup code.
2010-08-17configs: clean up checkpoint code in Simulation.pySteve Reinhardt
Small change to clean up some redundant code. Should not have any functional impact.
2010-08-17test: Update stats for python object iteration.Steve Reinhardt
Small changes in tests with data races due to new object creation order.
2010-08-17sim: clean up child handlingSteve Reinhardt
The old code for handling SimObject children was kind of messy, with children stored both in _values and _children, and inconsistent and potentially buggy handling of SimObject vectors. Now children are always stored in _children, and SimObject vectors are consistently handled using the SimObjectVector class. Also, by deferring the parenting of SimObject-valued parameters until the end (instead of doing it at assignment), we eliminate the hole where one could assign a vector of SimObjects to a parameter then append to that vector, with the appended objects never getting parented properly. This patch induces small stats changes in tests with data races due to changes in the object creation & initialization order. The new code does object vectors in order and so should be more stable.
2010-08-17sim: move iterating over SimObjects into Python.Steve Reinhardt
2010-08-17sim: fail on implicit creation of orphans via portsSteve Reinhardt
Orphan SimObjects (not in the config hierarchy) could get created implicitly if they have a port connection to a SimObject that is in the hierarchy. This means that there are objects on the C++ SimObject list (created via the C++ SimObject constructor call) that are unknown to Python and will get skipped if we walk the hierarchy from the Python side (as we are about to do). This patch detects this situation and prints an error message. Also fix the rubytester config script which happened to rely on this behavior.
2010-08-17sim: make Python Root object a singletonSteve Reinhardt
Enforce that the Python Root SimObject is instantiated only once. The C++ Root object already panics if more than one is created. This change avoids the need to track what the root object is, since it's available from Root.getInstance() (if it exists). It's now redundant to have the user pass the root object to functions like instantiate(), checkpoint(), and restoreCheckpoint(), so that arg is gone. Users who use configs/common/Simulate.py should not notice.
2010-08-17tests: update reference config.ini files for previous csetSteve Reinhardt
Rename 'responder_set' to 'use_default_range'.
2010-08-17bus: clean up default responder code.Steve Reinhardt
Clean up some minor things left over from the default responder change in rev 9af6fb59752f. Mostly renaming the 'responder_set' param to 'use_default_range' to actually reflect what it does... old name wasn't that descriptive in the first place, but now it really doesn't make sense at all. Also got rid of the bogus obsolete assignment to 'bus.responder' which used to be a parameter but now is interpreted as an implicit child assignment, and which was giving me problems in the config restructuring to come. (A good argument for not allowing implicit child assignments, IMO, but that's water under the bridge, I'm afraid.) Also moved the Bus constructor to the .cc file since that's where it should have been all along.
2010-08-14Inorder: Fix compilation of m5.fast.Gabe Black
printMemData is only used in DPRINTFs. If those are removed by compiling m5.fast, that function is unused, gcc generates a warning, that gets turned into an error, and the build fails. This change surrounds the function definition with #if TRACING_ON so it only gets compiled in if the DPRINTFs do to.
2010-08-13Merge with head.Gabe Black
2010-08-13CPU: Add readBytes and writeBytes functions to the exec contexts.Gabe Black
2010-08-13InOrder: Clean up some DPRINTFs that print data sent to/from the cache.Gabe Black
2010-08-13CPU: Tidy up endianness handling for mmapped "IPR"s.Gabe Black
2010-08-12util/m5/m5.c: ensure readfile() buffer pages are in page tableJoel Hestness
(and marked dirty, in case that matters) by touching them beforehand
2010-08-12TimingSimpleCPU: fix NO_ACCESS memory op handlingJoel Hestness
When a request is NO_ACCESS (x86 CDA microinstruction), the memory op doesn't go to the cache, so TimingSimpleCPU::completeDataAccess needs to handle the case where the current status of the CPU is Running and not DcacheWaitResponse or DTBWaitResponse
2010-08-08None, not noneNathan Binkert
2010-07-27.hgignore: added src/doxygenSteve Reinhardt
2010-07-27ARM: Add regression testsAli Saidi
2010-07-22Power: The condition register should be set or cleared upon a system callTimothy M. Jones
return to indicate success or failure.
2010-07-22LSQ Unit: After deleting part of a split request, set it to NULL so that itTimothy M. Jones
isn't accidentally deleted again later (causing a segmentation fault).
2010-07-22Port: Only indicate that a SimpleTimingPort is drained if its send event isTimothy M. Jones
not scheduled, as well as the transmit list being empty.
2010-07-22O3CPU: Fix a bug where stores in the cpu where never marked as split.Timothy M. Jones
2010-07-22Syscall: Don't close the simulator's standard file descriptors.Timothy M. Jones
2010-07-22O3CPU: O3's tick event gets squashed when it is switched out. When repeatedlyTimothy M. Jones
switching between O3 and another CPU, O3's tick event might still be scheduled in the event queue (as squashed). Therefore, check for a squashed tick event as well as a non-scheduled event when taking over from another CPU and deal with it accordingly.
2010-07-22Power: Provide a utility function to copy registers from one thread contextTimothy M. Jones
to another in the Power ISA.
2010-07-21stats: unify the two stats distribution type betterNathan Binkert
2010-07-21stats: cleanup a few small problems in statsNathan Binkert
2010-07-21python: add a sorted dictionary classNathan Binkert
It would be nice if python had a tree class that would do this for real, but since we don't, we'll just keep a sorted list of keys and update it on demand.
2010-07-21python: Add mechanism to override code compiled into the exectuableNathan Binkert
If the user sets the environment variable M5_OVERRIDE_PY_SOURCE to True, then imports that would normally find python code compiled into the executable will instead first check in the absolute location where the code was found during the build of the executable. This only works for files in the src (or extras) directories, not automatically generated files. This is a developer feature!
2010-07-21Fix x86 XCHG macro-op to use locked micro-ops for all memory accessesTushar Krishna
2010-07-17SimObject: transparently forward Python attribute refs to C++.Steve Reinhardt
This tidbit was pulled from a larger patch for Tim's sake, so the comment reflects functions that haven't been exported yet. I hope to commit them soon so it didn't seem worth cleaning up.
2010-07-15ARM: Make an SRS instruction with a bad mode cause an undefined instruction ↵Gabe Black
fault.
2010-07-13ARM: Adjust the FP_Base_DepTag to be larger than the largest int reg index.Gabe Black
2010-07-08cache: fix bug in SC upgrade handlingSteve Reinhardt
This bug was introduced with the recent rework of SC failure handling in cset f97b62be544f.
2010-07-08garnet: Added topology print function to Garnet printStatsBrad Beckmann