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2018-06-15mem-cache: Forward declare ReplaceableEntryDaniel R. Carvalho
Forward declare ReplaceableEntry where in classes where pointers to it are used. Change-Id: I49c08d36442a563d7a6b4c9bcd7eba3591d29b60 Reviewed-on: https://gem5-review.googlesource.com/11096 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-15dev-arm: Fix the address range for some I/O devicesNikos Nikoleris
Previously, many devices were incorrecty configured to respond to an address range of size 0xfff. This changes fixes this and sets it to 0x1000. Change-Id: I4b027a27adf60ceae4859e287d7f34443b398752 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11116 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-06-15tests,style: add RISC-V assembly testsTuan Ta
This patch adds a subset (rv64*) of RISC-V assembly tests. The original riscv-test project can be found here: https://github.com/riscv/riscv-tests. The riscv-test project is under the BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE) and is maintained separately from gem5 project. The tests have been slightly modified to work in gem5 SE mode: (1) Removed a trap handler used in riscv-tests for bare-metal systems (2) Instead of throwing an exception, the tests call the exit syscall with the exit code of - '0' if SUCCESS - Failed test case's number (non-zero) if FAILURE The exit code can be captured after a simuation completes. In addition to original RISC-V assembly tests, this patch adds several assembly tests specifically for AMO, LR, SC and system calls. Those tests target a multi-core system. (1) rv64uamt: multi-threaded tests for A-extension instructions (2) rv64samt: multi-threaded tests for clone and futex system calls This patch also makes the style checker ignore RISC-V assembly test directory. The assembly tests are maintained in an external project that does not follow the gem5 coding conventions. Please find more details in the README file included in this patch. Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0 Reviewed-on: https://gem5-review.googlesource.com/6703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-06-15sim: Add a SimObject python field which overrides the default c++ base.Gabe Black
The base for the c++ version of python SimObject classes is normally inferred from the c++ version of the python base. There are some specific cases where that isn't desired. This change makes it possible to override the default behavior. Change-Id: I2438dad767e2f56823bad42b3e6c7714ce97ef79 Reviewed-on: https://gem5-review.googlesource.com/10662 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-06-14cpu: Prevent suspended TimingSimple CPUs from fetching next instructionsTuan Ta
In TimingSimpleCPU model, when a CPU is suspended by a syscall (e.g., futex(FUTEX_WAIT)), the CPU waits for another CPU to wake it up (e.g., FUTEX_WAKE operation). While staying Idle, the suspended CPU should not try to fetch next instructions after the syscall. This patch added a status check before a CPU schedule a fetch event after a fault is handled. Change-Id: I0cc953135686c9b35afe94942aa1d0b245ec60a2 Reviewed-on: https://gem5-review.googlesource.com/8181 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-06-14cpu: add a new instruction type 'Atomic'Tuan Ta
This patch adds a new flag named 'Atomic' to support ISA implementations that use AtomicOpFunctor to handle atomic instructions instead of a pair of locking load and unlocking store. Change-Id: I1fbee6e54432396cb49dfc59ad9006b75812d115 Reviewed-on: https://gem5-review.googlesource.com/8187 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-06-14arch: support issuing Atomic Mem Operation (AMO) requestsTuan Ta
This patch adds two new functions named amoMemAtomic used in Atomic CPU model and initiateMemAMO used in Timing CPU models to issue AMO requests to the memory system. Change-Id: I962bdc0e5f25b72c170d96ebc136f29a2b230d5e Reviewed-on: https://gem5-review.googlesource.com/8186 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-06-14base,mem: Support AtomicOpFunctor in the classic memory systemTuan Ta
AtomicOpFunctor can be used to implement atomic memory operations. AtomicOpFunctor is captured inside a memory request and executed directly in the memory hierarchy in a single step. This patch enables AtomicOpFunctor pointers to be included in a memory request and executed in a single step in the classic cache system. This patch also makes the copy constructor of Request class do a deep copy of AtomicOpFunctor object. This prevents a copy of a Request object from accessing a deleted AtomicOpFunctor object. Change-Id: I6649532b37f711e55f4552ad26893efeb300dd37 Reviewed-on: https://gem5-review.googlesource.com/8185 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-14ruby: Revamp standalone SLICC scriptJason Lowe-Power
There was some bitrot in the standalone SLICC script (util/slicc and src/mem/slicc/main.py). Fix the changes to the SLICC interface and also add some better documentation. Change-Id: I91c0ec78d5072fba83edf32b661ae67967af7822 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/10561 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-14arch-arm: Adapting IllegalExecution fault for AArch32Giacomo Travaglini
The Illegal Execution fault triggered by the setting of processor state PSTATE.IL happens in AArch32 as well and takes the form of UNDEFINED exception fault. We are hence copying the UndefinedInstruction AArch32 fields into the IllegalInstSetStateFault. Change-Id: Ibb7424397c2030ea5d010577c530277a27036aea Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10814 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-06-14arch-arm: Add Illegal Execution flag to PCStateGiacomo Travaglini
This patch moves the detection of the Illegal Execution flag (PSTATE.IL) from the tlb translation stage (fetch) to the decoding stage. This is done by adding the illegalExecution field to the PCState. Change-Id: I9c1c4e9c6bd5ded905c1d56b3034e4e9322582fa Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10813 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-06-14arch-arm: Read APSR in User ModeGiacomo Travaglini
This patch substitutes reads to the CPSR in user mode (MRS CPSR) to reads to APSR (Application Program Status Register). This is the user level alias for the CPSR. The APSR is a subset of the CPSR. Change-Id: I18a70693aef6fd305a4c4cb3c6f81f331bc60a2d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10602 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-06-14system-arm: Split the VExpress_GEM5_V1 base dtsAndreas Sandberg
With the introduction of the new DPU model, we need different variations of the VExpress_GEM5_V1 platform. This splits the platform dtsi file into a separate file for the base platform and the HDLCD-based platform. This matches the hierarchy in RealView.py. Change-Id: Id02380122655b5d3aa3548a703fdef178bba17d9 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11035 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-06-14dev-arm: Add new VExpress_GEM5_V1_Base PlatformRohit Kurup
Add a new VExpress_GEM5_V1_Base Platform which configures basic on chip devices. The original VExpress_GEM5_V1 will inherit the Base and add more on chip devices (currently only the HDLCD). This change will make it possible to create variations of the base platform with different devices. Change-Id: I21f9bf4f6217d87e811ff777f630122593eef013 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10807 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-06-14cpu-minor: Remove redundant thread startup callAndreas Sandberg
Don't call startup() twice on each of the threads. Change-Id: Ibe3d1f25c4fdff291ee310abb9bcad3b184bab20 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11037
2018-06-14dev-arm: Remove deprecated GIC test interfacesAndreas Sandberg
Change-Id: I4c5203b216387d9a4f041c7a00caea926e5cfca6 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10810
2018-06-13tests: Make "UnitTest"s more like GTest so they can be in other dirs.Gabe Black
The original implementation of UnitTest forced all the output binaries to live in the unittest directory, effectively forcing a flat namespace, and seperating the tests from the things they were supposed to be testing. This changes makes them work more like the newer GTest tests in that they can be based out of whatever directory makes sense, although they're currently all still in unittest for the time being. This change also gets rid of automatically tagging the sources associated with a test with the tests name. The first reason for that was that this also forced a flat namespace, since the tests names didn't have any reference to the test's path. Second, this way of pulling in additional files wasn't necessary any more, now that the UnitTest sources could be source filters like they can be for GTests. Change-Id: I3d96ed766ac5170842dbd6daee39f2873bcd6c75 Reviewed-on: https://gem5-review.googlesource.com/10701 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-06-13mem-cache: Remove unnecessary cast in SectorTags::findVictimNikos Nikoleris
Removes an uneccessary cast that also caused an unused variable error (due to -Werror) when compiling .fast targets. Change-Id: Ic043f462925e7eaa7b691455f1d9e08a1c101980 Reviewed-on: https://gem5-review.googlesource.com/11119 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-13arch-arm: Fix missing Request allocationGiacomo Travaglini
This patch is fixing a missing allocation for a Request buffer in the Stage2Translation class. Change-Id: I9ce7b85d3527c5b3cc895eb83e9a39641793b0bd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11095 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-06-13mem-cache: Insert on block allocationDaniel R. Carvalho
When a block is being replaced in an allocation, if successfull, the block will be inserted. Therefore we move the insertion functionality to allocateBlock(). allocateBlock's signature has been modified to allow this modification. Change-Id: I60d17a83ff4f3021fdc976378868ccde6c7507bc Reviewed-on: https://gem5-review.googlesource.com/10812 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-13mem-cache: Make packet const in insertBlockDaniel R. Carvalho
The packet should not be modified within insertBlock. Change-Id: If7d2b01fe131f9923194efd155c9e85eeab24d5a Reviewed-on: https://gem5-review.googlesource.com/10811 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-13mem-cache: Create Sector CacheDaniel R. Carvalho
Implementation of Sector Caches, i.e., a cache with multiple sequential data entries per tag entry for Set Associtive placement policies. Change-Id: I8e1e9448fa44ba308ccb16cd5bcc5fd36c988feb Reviewed-on: https://gem5-review.googlesource.com/9741 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-12tests: add some pthread and std::thread unit testsTuan Ta
This patch adds some pthread and C++11 std::thread unit tests. Change-Id: I9706b542e5fa927a87c6e8ae2a6330fab7bb5d72 Reviewed-on: https://gem5-review.googlesource.com/8221 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-06-12ruby: Fix initial weight in weighted LRUDaniel R. Carvalho
Initial weight was using the timestamp instead of the weight. Change-Id: I61d3c8424f85fd6856957087c477afda111f8ca7 Reviewed-on: https://gem5-review.googlesource.com/10801 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-06-11misc: Using smart pointers for memory RequestsGiacomo Travaglini
This patch is changing the underlying type for RequestPtr from Request* to shared_ptr<Request>. Having memory requests being managed by smart pointers will simplify the code; it will also prevent memory leakage and dangling pointers. Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10996 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-11misc: Substitute pointer to Request with aliased RequestPtrGiacomo Travaglini
Every usage of Request* in the code has been replaced with the RequestPtr alias. This is a preparing patch for when RequestPtr will be the typdefed to a smart pointer to Request rather then a raw pointer to Request. Change-Id: I73cbaf2d96ea9313a590cdc731a25662950cd51a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10995 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-06-08mem-cache: Change Cache block tag checkDaniel R. Carvalho
Change tag to address check for compatibility with sector design. Cache should not use tag, as sector sub-blocks share them, and it could lead to wrong accesses. Change-Id: Id1fa26f417595f475c5b5c07ae1f02f5fa0684ba Reviewed-on: https://gem5-review.googlesource.com/10723 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-08mem-cache: Use secure bit in findVictimDaniel R. Carvalho
Sector caches must know if there was a sector hit in order to decide whether a victim's sector must be fully evicted to give place to a new sector or not. In order to do so it needs the tag and secure information. Change-Id: Ib554169e25fa131d6bf986561f7970b787c56874 Reviewed-on: https://gem5-review.googlesource.com/10722 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-08mem-cache: Move tagsInUse to childrenDaniel R. Carvalho
Move tagsInUse to children, as sector caches have different tag invalidation and insertion, and thus they must handle updating this variable. Change-Id: I875c9b7364a909c76daf610d1e226c4e82063870 Reviewed-on: https://gem5-review.googlesource.com/10721 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-08mem-cache: Return evictions along with victimsDaniel R. Carvalho
For both sector and compressed caches multiple blocks may need to be evicted in order to make room for a new block. For example, when replacing a sector, all the blocks in this sector must be evicted. A replacement, however, does not always need to evict multiple blocks, as it is in the case of an insertion of a block whose sector is already present in the cache (i.e., its corresponding entry in the sector had not been brought in yet, so it was invalid). This patch creates the cache framework for that to happen. Change-Id: I77bedf69637cf899fef4d9432eb6da8529ea398b Reviewed-on: https://gem5-review.googlesource.com/10142 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-08mem-cache: Use ReplaceableEntry in findBlockBySetAndWayDaniel R. Carvalho
With a sector cache you can't find a block using only its set and way, as there is the sector offset to take into account. As all of these blocks inherit from ReplaceableEntry, the return type of this function has been updated. This function has also been declared closer to findBlock() due to their similar functionality. Change-Id: I4730a2b4ebb5738f7fc118201e208a1b9c3ba8e8 Reviewed-on: https://gem5-review.googlesource.com/10141 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-08sim: Rename the SimObject cxx_bases field to cxx_extra_bases.Gabe Black
cxx_bases adds in additional c++ base classes beyond those implied by the python SimObject inheritance hierarchy. To imply the fact that these are additional bases, and to disambiguate a future mechanism which changes the implied bases, this flag/field is being renamed from cxx_bases to cxx_extra_bases. As far as I can tell, this field was only used internally in SimObject.py. Change-Id: Ie7cc3d0107ff71cc31424d6e20c9a2f430022ab9 Reviewed-on: https://gem5-review.googlesource.com/10661 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-06-07dev-arm: Add a VirtIO MMIO device to VExpress_GEM5_V1Andreas Sandberg
Add an ARM-specific VirtIO MMIO device to the VExpress_GEM5_V1 platform. Change-Id: Id1e75398e039aad9d637f46f653cda9084d3d2fe Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2327
2018-06-07dev-arm: Add a MMIO transport interface for VirtIOAndreas Sandberg
The MMIO interface currently only supports a subset of version 0.9.5 of the VirtIO specification. It has the following known limitations: * The queue size hint (the QUEUE_NUM register) is ignored. * Queue alignment is assumed to be hard-coded to VirtQueue::ALIGN_SIZE (4096 bytes). * Only 4096 byte pages are currently supported. Change-Id: Ifd318f5e5bddab0b6a42d8c8af9ff2fbb477f98b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2326 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-06-07dev-arm: Add a GIC interrupt adaptorAndreas Sandberg
Add GIC-based interrupt adaptor implementations that support PPI (ArmPPI) and SPI (ArmSPI) delivery. In addition to being useful for "normal" memory-mapped devices, the PPI adaptor makes it possible to use the same device model to generate both PPIs and SPIs (e.g., the PMU). Change-Id: I73d6591c168040faef2443430c4f1da10c387a2a Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2521 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-06-06arch-arm: Remove dead doingStage2 variable in PT walkerAndreas Sandberg
Change-Id: Iab5ecec56120c725847b2e462fd4793cfac87d3c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10815
2018-06-06system-arm: Update gem5 timer interrupt specificationAndreas Sandberg
The DTB for the VExpress_GEM5_V1 was incorrectly flagging timer interrupts as being edge triggered. Describe the interrupt as being level triggered to match Juno and FVP. Change-Id: I9ce4b8959e7cc28d8b208727119ff20e581311f8 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10024 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-06-06arch-arm: Perform stage 2 lookups using the EL2 stateAndreas Sandberg
Change-Id: Ic56b694f22a26e9c208a10e5703d4b5b0900070f Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10507 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-06-06arch-arm: Respect EL from translation typeAndreas Sandberg
There are cases where instructions request translations in the context of a lower EL. This is currently not respected in the TLB and the page table walker. Fix that. Change-Id: Icd59657a1ecfd8bd75a001bb1a4e41a6f4808a36 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10506 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-06-06arch-arm: Fix page size handling when merging stage 1 and 2Andreas Sandberg
The current code to merge translation entries from stage 1 and stage 2 doesn't handle cases where the page sizes at the different stages differ. This change fixes both the case when the hypervisor has a larger page size and when it has a smaller page size. Change-Id: Icdf289005bf1e4de4d91d54643924a38d9d77796 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10505 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-06-06dev, arm: Add support for HYP & secure timersAndreas Sandberg
Change-Id: I1a4849283f9bd5b1856e1378f7cefc33fc14eebd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10023 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-06-06arch-arm: Adjust breakpoint EC depending on source stateAndreas Sandberg
The software breakpoint exception class needs to be adjusted depending on the source EL's execution state. This change fixes an incorrect exception class when taking a breakpoint from aarch64. Change-Id: I99d87a04be6bf9ce3a69f6b19969fa006cfd63a4 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10809 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-06-01mem-cache: Privatize extractSetDaniel R. Carvalho
Only BaseSetAssoc uses extractSet(). Besides, skewed caches need the way information to know which set an address is located at. Change-Id: Id222e907dc550d053018561bb2683cfc415471ec Reviewed-on: https://gem5-review.googlesource.com/9962 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-01mem-cache: Create an address aware TempCacheBlkDaniel R. Carvalho
tempBlock has its member variables manually set in order to allow it to be used in the block address regeneration function. This is not necessary, and ti can be simply given the address, so it does not need to be aware of set and tag. This will simplify implementation of sector and skewed caches. Change-Id: Iaffb10c323509722cd5589fe1030b818d43336d6 Reviewed-on: https://gem5-review.googlesource.com/9961 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-01mem-cache: Fix secure bit modificationDaniel R. Carvalho
Secure bit was being updated outside insertion. Change-Id: I83d9b010e8cf64013bbea9bae3ea68b0c414a189 Reviewed-on: https://gem5-review.googlesource.com/10622 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-05-31mem-cache: Replace block visitor with std::functionNikos Nikoleris
This change modifies forEachBlk tags function to accept std::function as parameter. It also adds an anyBlk tags function that given a condition, it iterates through the blocks and returns whether the condition is met. Finally, it uses forEachBlk to implement the print, computeStats and cleanupRefs functions that also work for the FALRU class. Change-Id: I2f75f4baa1fdd5a1d343a63ecace3eb9458fbf03 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10621 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-05-31mem-cache: Fix include directives in the cache related classesNikos Nikoleris
Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c Reviewed-on: https://gem5-review.googlesource.com/10433 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-05-31mem-cache: Add a non-coherent cacheNikos Nikoleris
The class re-uses the existing MSHR and write queue. At the moment every single access is handled by the cache, even uncacheable accesses, and nothing is forwarded. This is a modified version of a changeset put together by Andreas Hansson <andreas.hansson@arm.com> Change-Id: I41f7f9c2b8c7fa5ec23712a4446e8adb1c9a336a Reviewed-on: https://gem5-review.googlesource.com/8291 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-05-31mem-cache: Move cache bypass mechanism to the portsNikos Nikoleris
Cache bypass is necessary for cpu models like the KvmCPU. Previously the bypass would happen at the cache classes. With this change the bypassing happens directly at the ports. Change-Id: I34de9fc63383aee8590643e169501ea6060d2d62 Reviewed-on: https://gem5-review.googlesource.com/10432 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-05-31mem-cache: Adopt a more sensible cache class hierarchyNikos Nikoleris
This patch changes what goes into the BaseCache and what goes into the Cache, to make it easier to add a NoncoherentCache with as much re-use as possible. A number of redundant members and definitions are also removed in the process. This is a modified version of a changeset put together by Andreas Hansson <andreas.hansson@arm.com> Change-Id: Ie9dd73c4ec07732e778e7416b712dad8b4bd5d4b Reviewed-on: https://gem5-review.googlesource.com/10431 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-20 16:56:24 +0000