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2012-07-09Port: Align port names in C++ and PythonAndreas Hansson
This patch is a first step to align the port names used in the Python world and the C++ world. Ultimately it serves to make the use of config.json together with output from the simulation easier, including post-processing of statistics. Most notably, the CPU, cache, and bus is addressed in this patch, and there might be other ports that should be updated accordingly. The dash name separator has also been replaced with a "." which is what is used to concatenate the names in python, and a separation is made between the master and slave port in the bus.
2012-07-09Bus: Make the default bus width 8 bytes instead of 64Andreas Hansson
This patch changes the default bus width to a more sensible 8 bytes (64 bits), which is in line with most on-chip buses. Although there are cases where a wider or narrower bus is useful, the 8 bytes is a good compromise to serve as the default. This patch changes essentially all statistics, and will be bundled with the outstanding changes to the bus.
2012-07-09Bus: Split the bus into separate request/response layersAndreas Hansson
This patch splits the existing buses into multiple layers. The non-coherent bus is split into a request and a response layer, and the coherent bus adds an additional layer for the snoop responses. The layer is modified to be templatised on the port type, such that the different layers can have retryLists with either master or slave ports. This patch also removes the dynamic cast from the retry, as previously promised when moving the recvRetry from the port base class to the master/slave port respectively. Overall, the split bus more closely reflects any modern on-chip bus and should be at step in the right direction. From this point, it would be reasonable straight forward to add separate layers (and thus contention points and arbitration) for each port and thus create a true crossbar. The regressions all produce the correct output, but have varying degrees of changes to their statistics. A separate patch will be pushed with the updates to the reference statistics.
2012-07-09Bus: Add a notion of layers to the busesAndreas Hansson
This patch moves all flow control, arbitration and state information into a bus layer. The layer is thus responsible for all the state transitions, and for keeping hold of the retry list. Consequently the layer is also responsible for the draining. With this change, the non-coherent and coherent bus are given a single layer to avoid changing any temporal behaviour, but the patch opens up for adding more layers.
2012-07-09Bus: Replace tickNextIdle and inRetry with a state variableAndreas Hansson
This patch adds a state enum and member variable in the bus, tracking the bus state, thus eliminating the need for tickNextIdle and inRetry, and fixing an issue that allowed the bus to be occupied by multiple packets at once (hopefully it also makes it easier to understand the code). The bus, in its current form, uses tickNextIdle and inRetry to keep track of the state of the bus. However, it only updates tickNextIdle _after_ forwarding a packet using sendTiming, and the result is that the bus is still seen as idle, and a module that receives the packet and starts transmitting new packets in zero time will still see the bus as idle (and this is done by a number of DMA devices). The issue can also be seen in isOccupied where the bus calls reschedule on an event instead of schedule. This patch addresses the problem by marking the bus as _not_ idle already by the time we conclude that the bus is not occupied and we will deal with the packet. As a result of not allowing multiple packets to occupy the bus, some regressions have slight changes in their statistics. A separate patch updates these accordingly. Further ahead, a follow-on patch will introduce a separate state variable for request/responses/snoop responses, and thus implement a split request/response bus with separate flow control for the different message types (even further ahead it will introduce a multi-layer bus).
2012-07-09Port: Make getAddrRanges constAndreas Hansson
This patch makes getAddrRanges const throughout the code base. There is no reason why it should not be, and making it const prevents adding any unintentional side-effects.
2012-07-09Port: Add getAddrRanges to master port (asking slave port)Andreas Hansson
This patch adds getAddrRanges to the master port, and thus avoids going through getSlavePort to be able to ask the slave. Similar to the previous patch that added isSnooping to the SlavePort, this patch aims to introduce an additional level of hierarchy in the ports (base port being protocol-agnostic) and getSlave/MasterPort will return port pointers to these base classes. The function is named getAddrRanges also on the master port, but does nothing besides asking the connected slave port. The slave port, as before, has to provide an implementation and actually produce a list of address ranges. The initial design used the name getSlaveAddrRanges for the new function, but the more verbose name was later changed.
2012-07-09Port: Add isSnooping to slave port (asking master port)Andreas Hansson
This patch adds isSnooping to the slave port, and thus avoids going through getMasterPort to be able to ask the master. Over the course of the next few patches, all getMasterPort/getSlavePort in Port and MemObject are to be protocol agnostic, and the snooping is part of the protocol layer. The function is already present on the master port, where it is implemented by the module itself, e.g. a cache. On the slave side, it is merely asking the connected master port. The same name is used by both functions despite their difference in behaviour. The initial design used isMasterSnooping on the slave port side, but the more verbose function name was later changed.
2012-07-09Port: Move retry from port base class to Master/SlavePortAndreas Hansson
This patch is the last part of moving all protocol-related functionality out of the Port base class. All the send/recv functions are already moved, and the retry (which still governs all the timing transport functions) is the only part that remained in the base class. The only point where this currently causes a bit of inconvenience is in the bus where the retry list is global and holds Port pointers (not Master/SlavePort). This is about to change with the split into a request/response bus and will soon be removed anyway. The patch has no impact on any regressions.
2012-07-09Fix: Address a few benign memory leaksAndreas Hansson
This patch is the result of static analysis identifying a number of memory leaks. The leaks are all benign as they are a result of not deallocating memory in the desctructor. The fix still has value as it removes false positives in the static analysis.
2012-07-02gcc: Fix warnings for gcc 4.7 and clang 3.1Andreas Hansson
This patch fixes two warnings, one related to a narrowing conversion (int to MachInst), and one due to the cast operator for arguments and a mismatch in const-ness (const void* and void*).
2012-06-29Cache: Fix the LRU policy for classic memory hierarchyLena Olson
The LRU policy always evicted the least recently touched way, even if it contained valid data and another way was invalid, as can happen if a block has been invalidated by coherance. This can result in caches never warming up even though they are replacing blocks. This modifies the LRU policy to move blocks to LRU position on invalidation.
2012-06-29Bus: enable non/coherent buses sub-classesUri Wiener
This patch merely changes several methods to be virtual in order to enable non/coherent buses sub-classes.
2012-06-29Mem: fix master id assertion in cache_impl.hhDam Sunwoo
The assertion was applied to the wrong packet. This patch fixes the issue rerported by Xiang Jiang on the gem5-dev mailing list.
2012-06-29Style: Make style.py's invalid warning print which file caused the infraction.Matt Evans
2012-06-29Mem: Fix a livelock resulting in LLSC/locked memory access implementation.Matt Evans
Currently when multiple CPUs perform a load-linked/store-conditional sequence, the loads all create a list of reservations which is then scanned when the stores occur. A reservation matching the context and address of the store is sought, BUT all reservations matching the address are also erased at this point. The upshot is that a store-conditional will remove all reservations even if the store itself does not succeed. A livelock was observed using 7-8 CPUs where a thread would erase the reservations of other threads, not succeed, loop and put its own reservation in again only to have it blown by another thread that unsuccessfully now tries to store-conditional -- no forward progress was made, hanging the system. The correct way to do this is to only blow a reservation when a store (conditional or not) actually /occurs/ to its address. One thread always wins (the one that does the store-conditional first).
2012-06-29Stats: Update stats for RAS and LRU fixes.Ali Saidi
2012-06-29O3: Track if the RAS has been pushed or not to pop the RAS if neccessary.Nathanael Premillieu
Add new flag (named pushedRAS) in the PredictorHistory structure. This flag tracks whether the RAS has been pushed or not during a prediction. Then, in the squash function it is used to pop the RAS if necessary.
2012-06-29ARM: Fix identification of one RAS pop instruction.Ali Saidi
The check should be with the op2 field, not with the op1 field.
2012-06-29Cache: Only invalidate a line in the cache when an uncacheable write is seen.Ali Saidi
2012-06-29ARM: Update version of linux we claim to be to 3.0.0.Ali Saidi
Static binaries generated with new versions of libc complain that the kernel is too old otherwise.
2012-06-29ARM: Fix issue with predicted next pc being wrong because of advance() ordering.Ali Saidi
npc in PCState for ARM was being calculated before the current flags were updated with the next flags. This causes an issue as the npc is incremented by two or four depending on the current flags (thumb or not) and was leading to branches that were predicted correctly being identified as mispredicted.
2012-06-27ARM: Fix address range issue with VExpress EMMAli Saidi
2012-06-20swig: Use SWIG from environment when determining versionAndreas Hansson
This patch fixes a minor issue in the SConstruct where a hardcoded swig is used instead of the environment SWIG when determining the version.
2012-06-18Build: Point to the appropriate tcmalloc packageAndreas Hansson
This patch updates the message printed if the user does not have tcmalloc available. It turns out that the correct package (which creates all required symlinks etc) is libgoogle-perftools-dev. This has been verified on Ubuntu 12.04.
2012-06-11configs: add run scripts for ics/gb versions of android and bbenchAnthony Gutierrez
1) Modifies Benchmarks.py to add support for Android ICS and BBench on Android ICS. 2) An rcS script is added for BBench on ICS. 3) Separates benchmark entries and rcS scripts for GB/ICS 4) Removes the debugging output from the existing BBench run script. These print statements were used for debugging and they seemed to confuse users into believing they should see some terminal output.
2012-06-11ARM: implement the ProcessInfo methodsAnthony Gutierrez
2012-06-11scons: Make compiler version error more verbose and easier to debug.Ali Saidi
2012-06-11Regression: Fix some bugs in simple-timing-mp-ruby.py.Marc Orr
2012-06-08Timing CPU: Remove a redundant port pointerAndreas Hansson
This patch is trivial and merely prunes a pointer that was never set or used.
2012-06-08Power: Fix MaxMiscDestRegs which was set to zeroAndreas Hansson
This patch fixes a failing compilation caused by MaxMiscDestRegs being zero. According to gcc 4.6, the result is a comparison that is always false due to limited range of data type.
2012-06-07X86 TLB: Add a missing = signNilay Vaish
2012-06-07mem: Delay deleting of incoming packets by one call.Ali Saidi
This patch is a temporary fix until Andreas' four-phase patches get reviewed and committed. Removing FastAlloc seems to have exposed an issue which previously was reasonable rare in which packets are freed before the sending cache is done with them. This change puts incoming packets no a pendingDelete queue which are deleted at the start of the next call and thus breaks the dependency between when the caller returns true and when the packet is actually used by the sending cache. Running valgrind on a multi-core linux boot and the memtester results in no valgrind warnings.
2012-06-07X86 TLB: Fix for gcc 4.4.3Jayneel Gandhi
Due to recent changes to X86 TLB, gem5 stopped compiling on gcc version 4.4.3. This patch provides the fix for that problem. The patch is tested on gcc 4.4.3. The change is not required for more recent versions of gcc (like on 4.6.3).
2012-06-07Config: call to setWorkCountOptions() for all ISAsNilay Vaish
2012-06-07Config: Remove setMipsOptionsNilay Vaish
As status matrix, MIPS fs does not work. Hence, these options are not required. Secondly, the function is setting param values for a CPU class. This seems strange, should probably be done in a different way.
2012-06-07Config: changes to a couple of error msgsNilay Vaish
2012-06-05cpu: Don't init simple and inorder CPUs if they are defered.Anthony Gutierrez
initCPU() will be called to initialize switched out CPUs for the simple and inorder CPU models. this patch prevents those CPUs from being initialized because they should get their state from the active CPU when it is switched out.
2012-06-05ISA: Back-out NoopMachInst as a StaticInstPtr change.Ali Saidi
2012-06-05cpt: update some comments in the checkpoint migration scriptAli Saidi
2012-06-05all: Update stats for memory per master and total fix.Ali Saidi
2012-06-05stats: when applying an operation to two vectors sum the components first.William Wang
Previously writing X/Y in a formula would result in: x[0]/y[0] + x[1]/y[1] In reality you want: (x[0] +x[1])/(y[0] + y[1])
2012-06-05Mem: add per-master stats to physmemDam Sunwoo
Added per-master stats (similar to cache stats) to physmem.
2012-06-05ARM: Add PCIe support to VExpress_EMM model and remove deprecated ELTGeoffrey Blake
2012-06-05ARM: removed extra white spaceChander Sudanthi
Extra white space fixes in miscregs.hh
2012-06-05ARM: Fix MPIDR and MIDR register implementation.Chander Sudanthi
This change allows designating a system as MP capable or not as some bootloaders/kernels care that it's set right. You can have a single processor MP capable system, but you can't have a multi-processor UP only system. This change also fixes the initialization of the MIDR register.
2012-06-05ARM: PS2 encoding fixChander Sudanthi
Fixed Disable encoding and added SetDefaults. See http://wiki.osdev.org/Mouse_Input for encodings.
2012-06-05sim: Provide a framework for detecting out of data checkpoints and migrating ↵Ali Saidi
them.
2012-06-05stats: Add stats unittest for total calculations.Ali Saidi
2012-06-05O3: Clean up the O3 structures and try to pack them a bit better.Ali Saidi
DynInst is extremely large the hope is that this re-organization will put the most used members close to each other.