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AgeCommit message (Expand)Author
2012-03-11se.py: Changes to ruby portion due to SE/FS mergeNilay Vaish
2012-03-11O3: Add fatal when fetchWidth > Impl::MaxWidth.Brian Grayson
2012-03-09ARM: Fix memory starting at non-zero address and exceeding max mem for a system.Ali Saidi
2012-03-09ARM: Update stats for CBNZ fix.Ali Saidi
2012-03-09ARM: Fix branch prediction issue with CB(N)Z instructionBrian Grayson
2012-03-09ARM: Update stats for valgrind fix and replace config.inis which are out of d...Ali Saidi
2012-03-09O3/Ozone: Eliminate dead code counting software prefetch instsGeoffrey Blake
2012-03-09CheckerCPU: Make some basic regression tests for CheckerCPUGeoffrey Blake
2012-03-09CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPUGeoffrey Blake
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
2012-03-09ARM: Don't reset CPUs that are going to be switched in.Ali Saidi
2012-03-09System: Move code in initState() back into constructor whenever possible.Ali Saidi
2012-03-09ARM: Fix valgrind reported error on O3 that was causing minor stats changes.Ali Saidi
2012-03-09cache: Allow main memory to be at disjoint address ranges.Ali Saidi
2012-03-08Fix the SPARC fs regression by adding a call to createInterruptController.Gabe Black
2012-03-06build scripts: Made minor modifications to reduce build overhead time.Marc Orr
2012-03-06Stats: Update stats for changeset 8868Andreas Hansson
2012-03-02SConstruct: rename and document AddM5OptionSteve Reinhardt
2012-03-02SConstruct: update comments & doc stringsSteve Reinhardt
2012-03-02DynInst: get rid of dead MyHash code.Steve Reinhardt
2012-03-02CPU: Check that the interrupt controller is created when neededAndreas Hansson
2012-03-02Stats: Fix the realview regression stats after nvmem moveAndreas Hansson
2012-03-02Ruby: Rename RubyPort::sendTiming to avoid overriding base classAndreas Hansson
2012-03-02ARM: FIx a bug preventing multiple cores booting a VExpress_EMM machine.Ali Saidi
2012-03-01ARM: FIx missing cf controller connection.Ali Saidi
2012-03-01VNC: spacingChander Sudanthi
2012-03-01ARM: Add support for Versatile Express extended memory mapAli Saidi
2012-03-01ARM: Add RTC device for ARM platforms.Ali Saidi
2012-03-01ARM: Add limited CP14 support.Matt Horsnell
2012-03-01Cache: Fix an issue with LRU when bonus block is used to complete transaction.Ali Saidi
2012-03-01ARM: move kernel func event to correct location.Dam Sunwoo
2012-03-01ARM: fix bits-to-fp conversion function declarations.Giacomo Gabrielli
2012-03-01x86: Fix x86 TLB and WalkerNilay Vaish
2012-03-01x86: Fix switching of CPUsNilay Vaish
2012-03-01Config: make option ruby available alwaysNilay Vaish
2012-02-29MEM: Make all the port proxy members constAndreas Hansson
2012-02-29SWIG: Ensure ptrdiff_t is a known type in gcc >= 4.6.1Andreas Hansson
2012-02-29EIO: update stats (mostly order change, some renames)Steve Reinhardt
2012-02-26Make the IO bridge accept address headed to all the local APICs.Gabe Black
2012-02-26X86: Use the M5PanicFault fault in execute methods instead of calling panic.Gabe Black
2012-02-24MEM: Simplify cache ports preparing for master/slave splitAndreas Hansson
2012-02-24MEM: Prepare mport for master/slave splitAndreas Hansson
2012-02-24Ruby: Simplify tester ports by not using SimpleTimingPortAndreas Hansson
2012-02-24MEM: Move all read/write blob functions from Port to PortProxyAndreas Hansson
2012-02-24MEM: Make port proxies use references rather than pointersAndreas Hansson
2012-02-24MEM: Move port creation to the memory object(s) constructionAndreas Hansson
2012-02-24CPU: Round-two unifying instr/data CPU ports across modelsAndreas Hansson
2012-02-24MEM: Fatal when no port can be found for an addressAndreas Hansson
2012-02-20SimObject: make get_config_as_dict() tolerate undefined paramsSteve Reinhardt
2012-02-14MEM: Fix residual bus ports and make them master/slaveAndreas Hansson