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The existing code was essentially doing the same thing, but in a more
roundabout and obscure way. One difference between the two versions is that
I believe this will stop as soon as it encounters an element without a
parent, where the original version would call has_parent() on all the
elements regardless.
Change-Id: Ia1fef3083fc88fca11f8ecfca453476e33194695
Reviewed-on: https://gem5-review.googlesource.com/4842
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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NullSimObject doesn't have a has_parent function, and it's not clear what its
return value should be if one were added. The appropriate value seems to
depend on why some other bit of code is checking if there's a parent in the
first place.
In SimObjectVector, the has_parent function is checking whether all of its
elements have a parent. In this particular case, the most reasonable thing
to do seems to be to just skip those elements.
Change-Id: I5f8cad66d1b22c5e37962492fd77cff9371e5af8
Reviewed-on: https://gem5-review.googlesource.com/4841
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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This lets attempts to set_parent on NullSimObject fall away harmlessly
without having to add a bunch of checks whenever set_parent is called.
Change-Id: I6d3510772ba71e765c4739e486e9f3d2460c4e11
Reviewed-on: https://gem5-review.googlesource.com/4840
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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This will let somebody consuming the memory packet trace make sense out of
the master IDs passed along with individual accesses.
Change-Id: I621d915f218728066ce95e6fc81f36d14ae7e597
Reviewed-on: https://gem5-review.googlesource.com/4800
Reviewed-by: Rahul Thakur <rjthakur@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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This map is intended to map from request MasterIDs to master names. It could
be used to map to arbitrary strings in other situations, however.
The original idea to store this information was to add a new message type
which would store one ID and the string associated with it. This change stores
the IDs in the header instead so that they'll be easy to find and all
available before the packet data.
One downside of this approach is that it won't be possible to add new master
ID strings as they come up during a trace. If that becomes an issue, the two
approaches could be combined and messages could be added which would augment
the map in the header.
Also worth mentioning is that the proto2 version of the protobuf description
language does not support the "map" field type, and the protoc compiler on my
workstation doesn't support proto3. Because that's such an appropriate
representation for this data, the map is represented in an equivalent format
described in the proto3 documentation.
Change-Id: I137c8611c33d9ce6589e196d50c8638c1d88750c
Reviewed-on: https://gem5-review.googlesource.com/4782
Reviewed-by: Rahul Thakur <rjthakur@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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There's a spot for it in the packet trace protobuf, so we should fill it
with something.
Change-Id: I784feb3f668e1b20d67b6ef98d012bcf59b7bd40
Reviewed-on: https://soc-sim-internal-review.googlesource.com/3483
Reviewed-by: Rahul Thakur <rjthakur@google.com>
Reviewed-on: https://gem5-review.googlesource.com/4781
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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That can be recorded in a packet trace.
Change-Id: I3813ab4ea5aadeb40b355ff01f10e8ecab2bb790
Reviewed-on: https://soc-sim-internal-review.googlesource.com/3482
Reviewed-by: Rahul Thakur <rjthakur@google.com>
Reviewed-on: https://gem5-review.googlesource.com/4780
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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* When dispatching multiple gem5 simulations at once, they race
for the socket id, resulting in a panic when calling 'bind'. To
avoid this problem, the socket id is now created before the diod
process is created. In case of a race, a panic is called in the
gem5 process, whereas before the panic was called in the diod
process where it didn't have any effect.
* In some cases killing the diod process in terminateDiod() using
only SIGTERM failed, so a call using SIGKILL is added.
Change-Id: Ie10741e10af52c8d255210cd4bfe0e5d761485d3
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2821
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The primary difference between loadState and unserialize, at least when
eventually using the default SimObject implementation of loadState, is that
unserialize is called only if there's a corresponding section in the
checkpoint being restored. In this particular case, the AlphaProcess class
calls the generic Process unserialize function, and that does other critical
initialization like set up the processes page table. If the unserialize
function isn't called, other serious problems would break the simulation
anyway.
This removes the final custom implementation of loadState.
Change-Id: If50062392196bd37efd5ba04fd7aee6907b00dc6
Reviewed-on: https://gem5-review.googlesource.com/4741
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The primary difference between using loadState and letting the default
implementation of loadState call unserialize is that whether or not that code
is called is dependent on that object being associated with a section in the
checkpoint file being unserialized. Since there's always a "root" object,
there should always be a section for it in the checkpoint and those should be
equivalent.
This removes one custom implementation of the loadState function.
Change-Id: Ia674ccc18e141f38746e22ccfddc21475b1a0731
Reviewed-on: https://gem5-review.googlesource.com/4740
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The MuxingKvmGic class defined a few functions related to checkpointing which
did nothing other than call the underlying Pl390 implementation. These are
unnecessary in general, and are particularly unnecessary for the loadState
function which is a very lightly used part of the checkpointing interface.
It's not actually defined in Pl390 either, and falls through to the
underlying implementation.
Change-Id: I84aae13d4966df0f4fdd1a72aee0bf1af01392ff
Reviewed-on: https://gem5-review.googlesource.com/4760
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Some simulators already set the time resolution of SystemC. By coupling
gem5 by means of SystemC with an other tool this can lead to problems:
When the resolution is set twice the simulation will not work.
Therefore, the line is changed to an assertion that checks if the time
resolution of the SystemC simulation is set to gem5's value of 1ps.
Change-Id: I8aafab9dd593eb4697a3c7f69ce181fd9cdd05c4
Reviewed-on: https://gem5-review.googlesource.com/4520
Reviewed-by: Paul Rosenfeld <prosenfeld@micron.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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This stat is only incremented by Alpha. Also move the _hwrei into the Alpha
stats object since it's the class that actually sets up and maintains that
value and it probably should have been there all along.
Change-Id: Ibd038a33230c01432c160490926d8e1e55f8ccb0
Reviewed-on: https://gem5-review.googlesource.com/4601
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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The kernel stat mechanism should really be refactored and moved somewhere
else, but in the mean time there's some old cruft that can be cleared away.
Change-Id: I21e725de590dda0d20bf3bc675bbe976c7b1bd86
Reviewed-on: https://gem5-review.googlesource.com/4600
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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When different sizes were set for the choice and global saturation
counter (e.g. ex5_big), the threshold calculation used the wrong
size. Thus the branch predictor always predicted "not taken" for
choice > global.
Change-Id: I076549ff1482e2280cef24a0d16b7bb2122d4110
Reviewed-on: https://gem5-review.googlesource.com/4560
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Coverage was wrongly set to PartialAddrRangeCoverage in the case of
disjoint adjacent ranges
Change-Id: I29aaf5145e6cdcf5f0b8f4e009d57ee57bd4c944
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/4640
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: Ic3652f975477f2e5d144e054489ab73ed9f82b55
Reviewed-on: https://gem5-review.googlesource.com/4440
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Joe Gross <joe.gross@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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When writing a bitmask of counters to PMSWINC, the PMU currently
increments the corresponding counters regardless of what they are
configured to count. According to the ARM ARM (D5.10.4), counters
should only be updated if they have been configured to count
software events (event type 0).
Change-Id: I5b2bc1fae55faa342b863721c9838342442831a9
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4285
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: I94a4bf4a633aeed550f8c01ccae824add3b85eb0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4284
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
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Change-Id: Ie5ef1aaaef46cf8ef8fa4b0fc8f7efb8cde9b489
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4283
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Recent gcc versions complain about a missing VecDisabled not having an
explicit FaultVals instantiation.
Change-Id: I439e7b3a7d5cad20590f52b3f374ead3f3f070a6
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4282
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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Change-Id: I3a52fcdb449c7df1612466270aa2c9b0a0f3afef
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4281
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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PyBind normally casts integers returned from the C to long in
Python. This is normally fine since long in most cases behaves just
like an int. However, when passing the return value from getcode() to
sys.exit, unexpected behavior ensues. Due to the way the function is
defined, any type other than int (with the exception of None) will be
treated as an error and be equivalent to sys.exit(1).
Since we frequently use the sys.exit(event.getCode()) pattern, we need
to ensure that the function returns an integer. This change adds an
explicit type conversion to a Python integer in the wrapper code.
Change-Id: I73d6b881025064afa2b2e6eb4512fa2a4b0a87da
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jose Marinho <jose.marinho@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4280
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Joe Gross <joe.gross@amd.com>
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When a split load hits a memory region where IPRs are mapped, the
Writebackevent which is scheduled for that was carrying a data packet
that was not correctly initialized which caused an assertion to fire
when the Writeback event is processed.
Change-Id: I71a4e291f0086f7468d7e8124a0a8f098088972f
Signed-off-by: Matthias Hille <matthiashille8@gmail.com>
Reported-by: Matthias Hille <matthiashille8@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/4620
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The condition is whether the control register index is valid.
Change-Id: I8a225fcfd4955032b5bbf7d3392ee5bcc7d6bc64
Reviewed-on: https://gem5-review.googlesource.com/4581
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
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A condition can be specified which will tell the decoder whether to return
the instruction being requested, or, if the condition fails, UD2.
Change-Id: I0f1c075deb10754ce1dd88be1726a196294e41fd
Reviewed-on: https://gem5-review.googlesource.com/4580
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
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The error message says an IDE controller can support at most 4 disks, but the
check would fail if there were more than 3 disks.
Change-Id: Ic7d5d8c941fe2580da43019f53991377d4727bb9
Reviewed-on: https://gem5-review.googlesource.com/4460
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Request and Packet for squashed HWPrefetches were not deleted
Change-Id: I9b66bb01b8ed6a5ddfaaa8739a68165dc4a7006c
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/4340
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
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The change "config: Change mem_range attribute naming in ARM
SimpleSystem" modified the SimpleSystem class to be compatible with
the MemConfig utility script. While doing so, the way we report the
memory ranges supported by the system changed, which broke the bL
example configration. This changeset introduces the necessary changes
to make the script work again.
Change-Id: I789987950ff04b6c5ae1c8b807355bcba34f6b3c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4380
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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The ARM example configs used to rely on CPU aliases for the
AtomicSimpleCPU and KVM when configuring clusters. This broken when
support for CPU aliases was removed ('config: Remove support for CPU
aliases.'). This change updates the config scripts to use the full
class names instead.
Change-Id: If36c46207f39ca1897ecf77d9588f1c059819e63
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4360
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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When asynchronous IO fails, gem5 currently just says it failed and quits, and
doesn't give any more information about which step failed, or what
specifically about it failed.
This change adds two helpers which will attempt the fcntl, check for error
conditions, and in the event of a failure, include a message describing the
error code and what the arguments to fcntl were.
Change-Id: I316478172ab2aefd3788279dbc12744791385cd5
Reviewed-on: https://gem5-review.googlesource.com/4320
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Change-Id: Ib2c7a7d26e7121dd082ca55a7c7ccf53fc47572c
Reviewed-on: https://gem5-review.googlesource.com/4240
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Teach the style checker about common headers living in gem5/. These
should be included after any global library headers (e.g., C headers
or STL headers), but before the normal gem5 headers.
Change-Id: I322f841420e361c16314be8fa4cbd1e86d2bfa9f
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4300
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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The header file with C declarations for m5ops is sometimes needed by
code outside of the util/m5 directory. Move this file to the shared
include directory and factor out flags to a generic asm header. Note
that applications that need to call m5ops still need to link with
libm5.a or implement their own trampolines.
Change-Id: I36a3f459ed71593e38b869dc2b1302c810f92276
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jose Marinho <jose.marinho@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4265
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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Rename m5op C symbols to be prefixed all lower case, separated by
underscore, and prefixed by m5. This avoids potential name clashes for
short names such as arm.
Change-Id: Ic42f94d8a722661ef96c151d627e31eeb2e51490
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jose Marinho <jose.marinho@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4264
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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Change-Id: I544519c4f87e50cc02af29cbb3edc31ecf726e8e
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4263
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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Use named constants from a shared header instead of magic values when
handling pseudo ops.
Change-Id: If157060bbcd772ce7e8556482b44ca714f4319b1
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4262
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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The header file m5ops.h contains a list of constants that should be
shared between the simulator and utilities. Move this header file to a
new top-level directory for shared files and rename constants to make
them suitable for inclusion in the main simulator.
The structure of the shared include directory is as follows:
include/gem5: Files that can be included from C code.
include/gem5/asm: Files that can be included from assembly code.
asm/generic/: Files that aren't guest ISA specific
asm/${isa}/: Files that are guest ISA specific
Change-Id: I1aa511057bcaa80cc2d566109ff26581558c4a41
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jose Marinho <jose.marinho@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4261
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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ISA devices typically run in the device event queue. Previously, we
assumed that devices would perform their own EQ migrations as
needed. This isn't ideal since it means we have different conventions
for IO devices and ISA devices. Switch to doing migrations in the KVM
CPU instead to make the behavior consistent.
Change-Id: I33b74480fb2126b0786dbdbfdcfa86083384250c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4288
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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The VM's event queue is normally used for devices in multi-core KVM
mode. Add a helper method, BaseKvmCPU::deviceEventQueue(), to access
this queue. This makes the intention of code migrating to device event
queues clearer.
Change-Id: Ifb10f553a6d7445c8d562f658cf9d0b1f4c577ff
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4287
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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The KVM CPU sometimes needs to access devices when drain() is
called. This typically happens on ARM when synchronizing devices that
use the system register interface. When called from drain(), the event
queue isn't locked since drain is called from the outside when the
simulator isn't servicing any events. In such cases, performing a
migration to the device's queue will unlock a mutex that isn't
locked. This typically results in a deadlock when resuming the system
since the lock will be in an undefined state.
Change-Id: Ibdcc2e034e916a929124f297e72aae306cf66728
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4286
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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Old ARM systems used to pass the machine type in the ATAGS list passed
to the kernel. This has been largely deprecated by the introduction of
device trees. Switch to the DTOnly machine type by default in gem5
since all new platforms and kernel will require this behavior.
Change-Id: Icfd085e4862863b4ef495566bfddbd11591866c3
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4260
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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The CpuConfig helper currently assumes that all timing models live in
the cores.arm package. This ignores the potential mismatch between the
target ISA and the ISA assumptions made by the timing models.
Instead of unconditionally listing all CPU models in cores.arm, list
timing models from cores.generic and cores.${TARGET_ISA}. This ensures
that the listed timing models support the ISA that gem5 is targeting.
Change-Id: If6235af2118889638f56ac4151003f38edfe9485
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3947
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Add a full system example configuration for the ARM Research Starter
Kit on System Modeling. More information can be found at:
http://www.arm.com/ResearchEnablement/SystemModeling
Change-Id: Ia32a28eb713ba7050d790327ba6dbb73ec33b53a
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
[ Minor cleanups and more documentation ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4203
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Add a full system example configuration for the ARM Research Starter
Kit on System Modeling. More information can be found at:
http://www.arm.com/ResearchEnablement/SystemModeling
Change-Id: Ifa40419d21923a32bb383d58466e421fe4260ddd
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
[ Minor cleanups and more documentation ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4202
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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The High-Performance In-order (HPI) CPU timing model is tuned to be
representative of a modern in-order ARMv8-A implementation. The HPI
core and its supporting simulation scripts, namely starter_se.py and
starter_fs.py (under /configs/example/arm/) are part of the ARM
Research Starter Kit on System Modeling. More information can be found
at: http://www.arm.com/ResearchEnablement/SystemModeling
Change-Id: I124bd06ba42d20abff09d447542b031d17eabe22
Signed-off-by: Ashkan Tousi <ashkan.tousimojarad@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4201
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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MemConfig.config() expects memory ranges to be defined in a particular
way. This patch changes the naming of the mem_range attribute in
SympleSystem to enable use of MemConfig for configuring the memory.
Change-Id: I4964c136e53a99c69ff5e086cacb929aa435168d
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4200
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Change-Id: I6fd660da3899de1f8c61bf012532ff0437467302
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4220
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Assign different pids to the different commands specified with the "--cmd"
flag to configs/example/se.py
Without this change, the following command line triggers
a "fatal: _pid 100 is already used" error:
command=$PWD/tests/test-progs/hello/bin/arm/linux/hello
./build/ARM/gem5.opt configs/example/se.py -n 2 -c "$command;$command"
Change-Id: If6f726481eb196d4f42680b6aa46364fce4190ed
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/4160
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
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Change-Id: I86229cedb206e10326cdee3f09a5c871e49c8d48
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3965
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