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AgeCommit message (Expand)Author
2012-06-05all: Update stats for memory per master and total fix.Ali Saidi
2012-06-05stats: when applying an operation to two vectors sum the components first.William Wang
2012-06-05Mem: add per-master stats to physmemDam Sunwoo
2012-06-05ARM: Add PCIe support to VExpress_EMM model and remove deprecated ELTGeoffrey Blake
2012-06-05ARM: removed extra white spaceChander Sudanthi
2012-06-05ARM: Fix MPIDR and MIDR register implementation.Chander Sudanthi
2012-06-05ARM: PS2 encoding fixChander Sudanthi
2012-06-05sim: Provide a framework for detecting out of data checkpoints and migrating ...Ali Saidi
2012-06-05stats: Add stats unittest for total calculations.Ali Saidi
2012-06-05O3: Clean up the O3 structures and try to pack them a bit better.Ali Saidi
2012-06-05sim: Add support for tcmalloc if it's installed and available.Ali Saidi
2012-06-05sim: Remove FastAllocAli Saidi
2012-06-05ARM: Fix over-eager assert in gic.Ali Saidi
2012-06-05stats: Provide a mechanism to get a callback when stats are dumped.Mitchell Hayenga
2012-06-05ARM: Fix compilation on ARM after Gabe's change.Ali Saidi
2012-06-04ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.Gabe Black
2012-06-04X86: Update stats for the CPUID change.Gabe Black
2012-06-04X86: Ensure that the CPUID instruction always writes its outputs.Gabe Black
2012-06-04X86: Ensure that the decoder's internal ExtMachInst is completely initialized.Gabe Black
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson
2012-05-09Stats: Fix stats to match output after changeset 8800b05e1cb3Andreas Hansson
2012-05-30gcc: Small fixes to compile with gcc 4.7Andreas Hansson
2012-05-30Bus: Remove redundant packet parameter from isOccupiedAndreas Hansson
2012-05-30Bus: Turn the PortId into a transport function parameterAndreas Hansson
2012-05-30Packet: Unify the use of PortID in packet and portAndreas Hansson
2012-05-30Packet: Updated comments for src and dest fieldsAndreas Hansson
2012-05-30Bridge: Split deferred request, response and sender stateAndreas Hansson
2012-05-28X86: Use the HandyM5Reg to avoid a register read and some logic in the TLB.Gabe Black
2012-05-27X86: Add a 32 bit hello world test binary.Gabe Black
2012-05-27X86: Move the GDT down to where it can be accessed in 32 bit mode.Gabe Black
2012-05-27X86: Truncate addresses to 32 bits except in 64 bit mode, not long mode.Gabe Black
2012-05-26ISA,CPU: Generalize and split out the components of the decode cache.Gabe Black
2012-05-26CPU: Merge the predecoder and decoder.Gabe Black
2012-05-25ISA: Make the decode function part of the ISA's decoder.Gabe Black
2012-05-25CPU: Simplify the implementation of the decode cache.Gabe Black
2012-05-25Decode: Make the Decoder class defined per ISA.Gabe Black
2012-05-24Cache: Remove dangling doWriteback declarationAndreas Hansson
2012-05-23Packet: Cleaning up packet command and attributeAndreas Hansson
2012-05-23Config: Use the attribute naming and include ports in JSONAndreas Hansson
2012-05-23DMA: Split the DMA device and IO device into seperate filesAndreas Hansson
2012-05-23MEM: Add a snooping DMA port subclass for table walkerAndreas Hansson
2012-05-23Config: Exit with fatal if a port is already connectedAndreas Hansson
2012-05-22X86 Regression: update stats due to cc register splitNilay Vaish
2012-05-22Ruby: Remove the unused src/mem/ruby/common/Driver.* files.Nilay Vaish
2012-05-22Ruby Sequencer: Schedule deadlock check event at correct timeNilay Vaish
2012-05-22X86: Split Condition Code registerNilay Vaish
2012-05-19x86 ISA: Implement the sse3 haddps instruction.Marc Orr
2012-05-19Syscalls: warn when the length argument to mmap is excessive.Gabe Black
2012-05-14Mem: Fix size check when allocating physical memoryLena Olson
2012-05-16Config: Fix a typo in the se.py script for setting fastmemAndreas Hansson