| Age | Commit message (Collapse) | Author |
|---|
|
|
|
|
|
|
|
|
|
|
|
It runs out that if a MemObject turns around and does a send in its
receive callback, and there are other sends already scheduled, then
it could observe a state where it's not at the head of the list but
the bus's sendEvent is not scheduled (because we're still in the
middle of processing the prior sendEvent).
|
|
I was asserting that the only reason you would defer targets is if
a write came in while you had an outstanding read miss, but there's
another case where you could get a read access after you've snooped
an invalidation and buffered it because it applies to a prior
outstanding miss.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
"behind" the pci config magic ports.
|
|
|
|
|
|
|
|
|
|
classes.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
variant of iret.
|
|
|
|
|
|
|
|
|
|
|
|
Instead of computing the segment descriptor address, this now checks if a
selector value/descriptor are legal for a particular purpose.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
than one register is accessed at a time.
|
|
calculating it.
|
|
|
