summaryrefslogtreecommitdiff
AgeCommit message (Expand)Author
2013-01-07config: Do not use hardcoded physmem in fs scriptAndreas Hansson
2013-01-07mem: Tidy up bus addr range debug messagesAndreas Hansson
2013-01-07mem: Skip address mapper range checks to allow more flexibilityAndreas Hansson
2013-01-07base: Encapsulate the underlying fields in AddrRangeAndreas Hansson
2013-01-07mem: Remove the joining of neighbouring rangesAndreas Hansson
2013-01-07cpu: Share the send functionality between traffic generatorsAndreas Hansson
2013-01-07cpu: Add support for protobuf input for the trace generatorAndreas Hansson
2013-01-07tests: Add support for skipping tests, skip EIO tests if not enabledAndreas Sandberg
2013-01-07cpu: Encapsulate traffic generator input in a streamAndreas Hansson
2013-01-07base: Add wrapped protobuf input streamAndreas Hansson
2013-01-07mem: Add tracing support in the communication monitorAndreas Hansson
2013-01-07base: Add wrapped protobuf output streamsAndreas Hansson
2013-01-07scons: Add support for google protobuf buildingAndreas Hansson
2013-01-07arm: Fix DMA event handling bug in the PL111 modelAndreas Sandberg
2013-01-07dev: Fix the Pl111 timings by separating pixel and DMA clockAndreas Hansson
2013-01-07stats: Update DRAM regression stats to match new configAndreas Hansson
2013-01-07config: Reduce DRAM controller regression traffic rateAndreas Hansson
2013-01-07cpu: Fix the traffic gen read percentageAndreas Hansson
2013-01-07mem: Add sanity check to packet queue sizeAndreas Hansson
2013-01-07ruby: Fix missing cxx_header in SwitchAndreas Hansson
2013-01-07scons: Fix libelf linking errors when using clang/llvmAndreas Hansson
2013-01-07config: Replace second keyboard with a mouse.Chris Emmons
2013-01-07mem: Fix a bug in the memory serialization file namingAndreas Hansson
2013-01-07arm: Make ID registers ISA parametersAndreas Sandberg
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
2013-01-07o3: Fix issue with LLSC ordering and speculationAli Saidi
2013-01-07cpu: rename the misleading inSyscall to noSquashFromTCAli Saidi
2013-01-07tests: Always specify memory mode in every test system.Ali Saidi
2013-01-07tests: Create base classes to encapsulate common test configurationsAndreas Sandberg
2013-01-07cache: add note about where conflicts are handledAli Saidi
2013-01-04regressions: stats update due to decoder changesNilay Vaish
2013-01-04Decoder: Remove the thread context get/set from the decoder.Gabe Black
2013-01-04X86: Move address based decode caching in front of the predecoder.Gabe Black
2013-01-04SPARC: Keep a copy of the current ASI in the decoder.Gabe Black
2013-01-04ARM: Keep a copy of the fpscr len and stride fields in the decoder.Gabe Black
2012-12-30x86 regressions: stats update due to new x87 instructionsNilay Vaish
2012-12-30x86: implement x87 fp instruction fnstswNilay Vaish
2012-12-30x86: implement x87 fp instruction fsincosNilay Vaish
2012-12-12arm regressions: updates to config.ini, terminal filesNilay Vaish
2012-12-12arm: set uopSet_uop as conditional or unconditional controlNathanael Premillieu
2012-12-12arm: set movret_uop as conditional or unconditional controlNathanael Premillieu
2012-12-11regressions: stats update due to stats from ruby prefetcherNilay Vaish
2012-12-11ruby: add support for prefetching to MESI protocolNilay Vaish
2012-12-11ruby: modify the directed tester to read/write streamsNilay Vaish
2012-12-11ruby: change slicc to allow for constructor argsNilay Vaish
2012-12-11ruby: add a prefetcherNilay Vaish
2012-12-11ruby: add functions for computing next stride/page addressNilay Vaish
2012-12-06regression test: update a couple of config.ini filesNilay Vaish
2012-12-06TournamentBP: Fix some bugs with table sizes and countersErik Tomusk
2012-12-06inorder cpu: add missing DPRINTF argumentMalek Musleh