Age | Commit message (Collapse) | Author |
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extra : convert_revision : 26dad6853feaf4f68907aab902c54259281cac1c
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src/cpu/ozone/cpu.hh:
Fixes to get OzoneCPU working in SE/FS again.
src/cpu/ozone/cpu_impl.hh:
Be sure to set up ports properly.
src/cpu/ozone/front_end.hh:
Allow port to be created without specifying its name at the beginning.
src/cpu/ozone/front_end_impl.hh:
Setup port properly, also only use checker if it's enabled.
src/cpu/ozone/lw_back_end_impl.hh:
Be sure to initialize variables.
src/cpu/ozone/lw_lsq.hh:
Handle locked flag for UP systems.
src/cpu/ozone/lw_lsq_impl.hh:
Initialize all variables.
src/python/m5/objects/OzoneCPU.py:
Fix up config.
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extra : convert_revision : c99e7bf82fc0dd1099c7a82eaebd58ab6017764d
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src/cpu/o3/cpu.cc:
Updates to make sure the checker is compiled in if enabled and also to include it only when it's used.
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The changes largely are fixing up the memory accesses to use ports/Requests/Packets, supporting the splitting off of instantiation of template classes, and handling some of the reorganization that happened.
OzoneCPU is untested for now but at least compiles. Fixes will be coming shortly.
SConstruct:
Remove OzoneSimpleCPU from list of CPUs.
src/cpu/SConscript:
Leave out OzoneSimpleCPU.
src/cpu/ozone/bpred_unit.cc:
Fixes to get OzoneCPU to compile.
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu.cc:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_builder.cc:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/dyn_inst.hh:
src/cpu/ozone/dyn_inst_impl.hh:
src/cpu/ozone/front_end.cc:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/ozone_impl.hh:
src/cpu/ozone/rename_table.cc:
src/cpu/ozone/simple_params.hh:
src/cpu/ozone/thread_state.hh:
Fixes to get OzoneCPU back to compiling.
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--HG--
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src/cpu/o3/alpha_dyn_inst_impl.hh:
Consolidate these calls into one.
src/cpu/o3/commit_impl.hh:
Include checker only if it's being used.
src/cpu/o3/fetch_impl.hh:
Do not deallocate request if it's a squashed response that was received.
src/cpu/o3/lsq_unit.hh:
Add in comment.
src/cpu/o3/lsq_unit_impl.hh:
Only include checker if it's being used.
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into tpx31.:C:/cygwin/home/stever/bk/newmem
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into zeep.eecs.umich.edu:/z/saidi/work/m5.newmem
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extra : convert_revision : 1b2352532b6e1d1e180f3debd66588a450a46923
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configs/test/SysPaths.py:
remove some tabs and add /n/poolfs/z/dist/m5/system
src/dev/io_device.cc:
fix since pio timing dma packts colud be nacked too
src/dev/io_device.hh:
move DmaReqState into DmaDevie
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extra : convert_revision : 2b5300d85ab33b3753afc54bc6a04a47b6e00d20
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src/cpu/o3/alpha_cpu.hh:
Fix #define in header.
util/rundiff:
Fix file comments to be more correct.
util/tracediff:
Update comments to be more correct.
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extra : convert_revision : a28030ce8979de3d9361191c6af23743460dc53e
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
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extra : convert_revision : a11200523e2cf7f69547b1a4f5622396caa511be
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Update release scripts for new tree structure.
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
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src/python/m5/__init__.py:
Change up options. Now setting the flag enables/disables, each of which is the opposite of the default values found in the Python class.
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SConstruct:
Remove check for Checker from this SConstruct
src/arch/SConscript:
Specific check if CheckerCPU is being used. Not the cleanest, but works for now.
src/cpu/SConscript:
Code to handle using the CheckerCPU a little better. Allows -c to be used normally.
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extra : convert_revision : 0a82f16db0f38e5ce114d08368477bd211331fa3
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makes it easier to be able to specify only certain CPU models.
src/cpu/SConscript:
Split off instantiations into separate CC files. This makes it easier to split them per CPU model.
src/cpu/base_dyn_inst_impl.hh:
Move instantations out of impl.hh file and into a cc file.
src/cpu/checker/cpu_impl.hh:
Move instantiations over to .cc files inside each CPU's directory. Makes it easier to only use what's actually included.
src/cpu/o3/bpred_unit.cc:
Pull Ozone instantiations out of this .cc file; put them into the ozone's CC file.
src/cpu/o3/checker_builder.cc:
Instantiate Checker for O3 CPU.
src/cpu/ozone/checker_builder.cc:
Instantiate Checker for Ozone CPU.
--HG--
rename : src/cpu/base_dyn_inst.cc => src/cpu/base_dyn_inst_impl.hh
rename : src/cpu/checker/cpu.cc => src/cpu/checker/cpu_impl.hh
rename : src/cpu/checker/o3_builder.cc => src/cpu/o3/checker_builder.cc
rename : src/cpu/checker/ozone_builder.cc => src/cpu/ozone/checker_builder.cc
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into zeep.eecs.umich.edu:/z/saidi/work/m5.newmem
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src/dev/alpha_console.cc:
Remove my name twice from header
src/dev/ide_disk.cc:
Spell my full name correctly
src/mem/bus.hh:
I think I edited much of this
src/sim/byteswap.hh:
I believe most of this code is mine or nate's
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into tpx31.:C:/cygwin/home/stever/bk/newmem
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extra : convert_revision : 81affa14d8d900ccd3d1c44cb160eaecfb8599d1
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src/kern/linux/linux.hh:
src/kern/solaris/solaris.hh:
Rename BSD_HOST to the more specific NO_STAT64.
src/sim/byteswap.hh:
Replace set of swap_byte functions with a single
templated version. Hope this fixes compiler issues
with e.g. int32_t vs int disambiguation.
src/sim/syscall_emul.hh:
Rename BSD_HOST to the more specific NO_STAT64.
Set this for __CYGWIN__.
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extra : convert_revision : 86a63b4b60d2445a566321333381d79ba8ab63c4
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configs/test/SysPaths.py:
Make the paths more configurable
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into iceaxe.:/Volumes/work/research/m5/newmem
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into zeep.eecs.umich.edu:/z/saidi/work/m5.newmem
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extra : convert_revision : c8670f1a39d6826870ca0934587f4cc71c94b0ab
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clear from the Python side that this is the
interface to C++.
src/SConscript:
main_wrap.cc -> cc_main_wrap.cc
src/python/SConscript:
src/python/m5/__init__.py:
src/sim/main.cc:
s/main/cc_main/
src/python/m5/config.py:
s/main/cc_main/
Also directly import cc_main so we don't need
to put the "m5." in front all the time.
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extra : convert_revision : 755552f70cf671881ff31e476c677b95ef12950d
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that's already being used for "detailed cpu".
Needed to add extra function for user script
to pass parsed options back to m5 module.
configs/test/fs.py:
configs/test/test.py:
Call setStandardOptions().
src/python/m5/__init__.py:
Add --outdir option.
Add setStandardOptions() so user script can
pass parsed options back to m5 module.
src/sim/main.cc:
Add SWIG-wrappable function to set output dir.
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extra : convert_revision : 1323bee69ca920c699a1cd1218e15b7b0875c1e5
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SConstruct:
Fix paths in comments and other minor comment edits.
src/cpu/SConscript:
Fix path in comment.
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extra : convert_revision : c02aa9cefd8c5ad791ad2f1653c1554a4aa8ffbd
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src/python/m5/__init__.py:
Add in some of the commonly used Trace/ExeTrace/Debug options. Not terribly clean but it works.
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
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directory and into the normal cpu directory.
src/SConscript:
Split off FuncUnits from old FUPool so I'm not including encumbered code. This was all written by Steve Raasch so it's safe to include in the main tree.
src/cpu/o3/fu_pool.cc:
Include the func unit file that's not in the encumbered directory.
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extra : convert_revision : 9801c606961dd2d62dba190d13a76069992bf241
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describes the ExecContext interface that the ISA uses to access CPU state. Also #ifdef Erik's old copy code from the decoder so ExecContext doesn't need his two specific copy functions.
src/arch/alpha/isa/decoder.isa:
Surround Erik's old copy code with #ifdefs. This way the copy functions don't need to be included in the ExecContext (until somebody decides to add them back in).
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src/cpu/checker/cpu.cc:
Add in comment.
src/cpu/cpuevent.hh:
Fix up comment.
src/cpu/o3/bpred_unit.cc:
Comment out Ozone instantiations.
src/cpu/o3/dep_graph.hh:
Include destructor.
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extra : convert_revision : 549454ed11bc2fa49a0627f7fb8f96d00a9be303
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pretty simple so they shouldn't cause any trouble.
First: Rename FullCPU and its variants in the o3 directory to O3CPU to differentiate from the old model, and also to specify it's an out of order model.
Second: Include build options for selecting the Checker to be used. These options make sure if the Checker is being used there is a CPU that supports it also being compiled.
SConstruct:
Add in option USE_CHECKER to allow for not compiling in checker code. The checker is enabled through this option instead of through the CPU_MODELS list. However it's still necessary to treat the Checker like a CPU model, so it is appended onto the CPU_MODELS list if enabled.
configs/test/test.py:
Name change for DetailedCPU to DetailedO3CPU. Also include option for max tick.
src/base/traceflags.py:
Add in O3CPU trace flag.
src/cpu/SConscript:
Rename AlphaFullCPU to AlphaO3CPU.
Only include checker sources if they're necessary. Also add a list of CPUs that support the Checker, and only allow the Checker to be compiled in if one of those CPUs are also being included.
src/cpu/base_dyn_inst.cc:
src/cpu/base_dyn_inst.hh:
Rename typedef to ImplCPU instead of FullCPU, to differentiate from the old FullCPU.
src/cpu/cpu_models.py:
src/cpu/o3/alpha_cpu.cc:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_cpu_impl.hh:
Rename AlphaFullCPU to AlphaO3CPU to differentiate from old FullCPU model.
src/cpu/o3/alpha_dyn_inst.hh:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/alpha_impl.hh:
src/cpu/o3/alpha_params.hh:
src/cpu/o3/commit.hh:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/rename.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rob.hh:
src/cpu/o3/rob_impl.hh:
src/cpu/o3/thread_state.hh:
src/python/m5/objects/AlphaO3CPU.py:
Rename FullCPU to O3CPU to differentiate from old FullCPU model.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
Rename FullCPU to O3CPU to differentiate from old FullCPU model.
Also #ifdef the checker code so it doesn't need to be included if it's not selected.
--HG--
rename : src/cpu/checker/o3_cpu_builder.cc => src/cpu/checker/o3_builder.cc
rename : src/cpu/checker/cpu_builder.cc => src/cpu/checker/ozone_builder.cc
rename : src/python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaO3CPU.py
extra : convert_revision : 86619baf257b8b7c8955efd447eba56e0d7acd6a
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src/cpu/checker/cpu.cc:
src/cpu/checker/cpu.hh:
Updates for checker. Output more informative messages on error. Rename some functions. Add in option to warn (and not exit) on load results being incorrect.
src/cpu/checker/cpu_builder.cc:
src/cpu/checker/o3_cpu_builder.cc:
Add in parameter to warn (and not exit) on load result errors.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
Renamed checker functin.
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(i.e. Sparc & MIPS)
Still need to add some code to fetch & commit stages
src/cpu/o3/commit.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
Add nextNPC read & set functions
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
Add nextNPC
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into zeep.eecs.umich.edu:/z/saidi/work/m5.newmem
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into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
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Key was adding support for cloning port references (trickier than it sounds).
Got rid of class/instance thing and go back to instance cloning...
still don't allow changing SimObject parameters/children after a
class (instance) has been subclassed or instantiated (or cloned), which
should avoid bizarre unintended behavior.
configs/test/fs.py:
Add ".port" to busses to get a port reference.
Get rid of commented-out code.
src/python/m5/__init__.py:
resolveSimObject should call getCCObject() instead of createCCObject()
to avoid cycles in recursively creating objects.
src/python/m5/config.py:
Get rid of class/instance thing and go back to instance cloning.
Deep copy has to happen only on instance cloning then (and not on subclassing).
Add getCCObject() method to force creation of C++ SimObject without
recursively creating its children.
Add support for cloning port references (trickier than it sounds).
Also clean up some very obsolete comments.
src/python/m5/objects/Bridge.py:
src/python/m5/objects/Device.py:
Add ports.
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extra : convert_revision : 4816d05ead0de520748aace06dbd1911a33f0af8
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Fix some author stuff and copyright dates
Take out full system code
src/arch/mips/isa/base.isa:
src/arch/mips/isa/bitfields.isa:
copyright info
src/arch/mips/isa/decoder.isa:
src/arch/mips/isa/formats/basic.isa:
src/arch/mips/isa/formats/branch.isa:
src/arch/mips/isa/formats/control.isa:
src/arch/mips/isa/formats/fp.isa:
src/arch/mips/isa/formats/int.isa:
src/arch/mips/isa/formats/mem.isa:
src/arch/mips/isa/formats/noop.isa:
src/arch/mips/isa/formats/tlbop.isa:
src/arch/mips/isa/formats/trap.isa:
src/arch/mips/isa/formats/unimp.isa:
src/arch/mips/isa/formats/unknown.isa:
src/arch/mips/isa/formats/util.isa:
src/arch/mips/isa/includes.isa:
src/arch/mips/isa/main.isa:
src/arch/mips/isa/operands.isa:
src/arch/mips/process.cc:
src/arch/mips/regfile/misc_regfile.hh:
src/arch/mips/stacktrace.hh:
copyright 2006
src/arch/mips/isa_traits.cc:
src/arch/mips/isa_traits.hh:
copyright 2006
take out full system
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/regfile/regfile.hh:
copyright 2006
use FloatRegVal
src/arch/mips/regfile/int_regfile.hh:
copyright 2006
move HI/LO to types.hh
src/arch/mips/types.hh:
copyright 2006
typedef FloatRegVal
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