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2016-02-06style: eliminate explicit boolean comparisonsSteve Reinhardt
Result of running 'hg m5style --skip-all --fix-control -a' to get rid of '== true' comparisons, plus trivial manual edits to get rid of '== false'/'== False' comparisons. Left a couple of explicit comparisons in where they didn't seem unreasonable: invalid boolean comparison in src/arch/mips/interrupts.cc:155 >> DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");<< invalid boolean comparison in src/unittest/unittest.hh:110 >> "EXPECT_FALSE(" #expr ")", (expr) == false)<<
2016-02-06x86: create function to check miscreg validitySteve Reinhardt
In the process of trying to get rid of an '== false' comparison, it became apparent that a slightly more involved solution was needed. Split this out into its own changeset since it's not a totally trivial local change like the others.
2016-02-06util: fix apparent statetrace bugSteve Reinhardt
In the process of trying to eliminate boolean comparisons, I ran across this statement that appears to be a bug (should have been an assignment).
2016-02-06util: added line length and boolean comparison style checkersSteve Reinhardt
Added checkers for line length and boolean comparisons (== true/== false) to the style script.
2016-02-06style: fix missing spaces in control statementsSteve Reinhardt
Result of running 'hg m5style --skip-all --fix-control -a'.
2016-02-06style: remove trailing whitespaceSteve Reinhardt
Result of running 'hg m5style --skip-all --fix-white -a'.
2016-02-06util: clean up and extend style checkerSteve Reinhardt
Added a new Verifier object to check for and fix spacing between if/while/for and following paren. Restructured Verifier class to make it easier to add new subclasses, particularly by using a global list of verifiers to auto-generate command line options and simplify the invocation loop.
2016-02-06util: delete old unused style-checking scriptsSteve Reinhardt
The functions in these scripts were apparently folded into style.py but the old scripts were orphaned without being deleted. Get rid of them so their existence is no longer confusing.
2016-02-06dist, dev: add an ethernet switch modelMohammad Alian
2016-02-06stats: update EIO stats for recent changesSteve Reinhardt
2016-02-04ext: fix SST connectorCurtis Dunham
Should work with SST 5.1 and trunk as of right now.
2016-01-29ext: remove redundant parameter in example SST+gem5 testCurtis Dunham
The SST connector automatically adds --initialize-only to the gem5 "command line" (as it should); the config script doesn't need it.
2016-01-29ext: Update NoMali to external rev f08e0a5Andreas Sandberg
Update NoMali from external revision 9adf9d6 to f08e0a5 and bring in the following changes: f08e0a5 Add support for tracking address space state f11099e Fix job slot register handling when running new jobs b28c98e api: Add a reset callback 29ac4c3 tests: Update gitignore to cover all future test cases 1c6b893 Propagate reset calls to all job slots 8f8ec15 Remove redundant reg vector in MMU 85d90d2 tests: Fix incorrect extern declaration
2016-01-22stats: update stats to after GPU checkinTony Gutierrez
2016-01-22ruby: removed Write_Only AccessPermissionBrad Beckmann
2016-01-22ruby: changed all references to numCPs to num-cpBrad Beckmann
2015-07-20ruby: split CPU and GPU latency statsDavid Hashe
2016-01-19gpu-compute: AMD's baseline GPU modelTony Gutierrez
2016-01-19mem: write combining for ruby protocolsTony Gutierrez
This patch adds support for write-combining in ruby.
2016-01-19* * *Tony Gutierrez
mem: support for gpu-style RMWs in ruby This patch adds support for GPU-style read-modify-write (RMW) operations in ruby. Such atomic operations are traditionally executed at the memory controller (instead of through an L1 cache using cache-line locking). Currently, this patch works by propogating operation functors through the memory system.
2015-07-20mem: misc flags for AMD gpu modelBlake Hechtman
This patch add support to mark memory requests/packets with attributes defined in HSA, such as memory order and scope.
2016-01-17sim: fix redundant --debug-start help stringSteve Reinhardt
Just changes the metavar for --debug-start from TIME to TICK in cset 72046b9b3323 and didn't notice that the comment "must be in ticks" is now redundant.
2016-01-17cpu. arch: add initiateMemRead() to ExecContext interfaceSteve Reinhardt
For historical reasons, the ExecContext interface had a single function, readMem(), that did two different things depending on whether the ExecContext supported atomic memory mode (i.e., AtomicSimpleCPU) or timing memory mode (all the other models). In the former case, it actually performed a memory read; in the latter case, it merely initiated a read access, and the read completion did not happen until later when a response packet arrived from the memory system. This led to some confusing things, including timing accesses being required to provide a pointer for the return data even though that pointer was only used in atomic mode. This patch splits this interface, adding a new initiateMemRead() function to the ExecContext interface to replace the timing-mode use of readMem(). For consistency and clarity, the readMemTiming() helper function in the ISA definitions is renamed to initiateMemRead() as well. For x86, where the access size is passed in explicitly, we can also get rid of the data parameter at this level. For other ISAs, where the access size is determined from the type of the data parameter, we have to keep the parameter for that purpose.
2016-01-17cpu: remove unnecessary data ptr from O3 internal read() funcsSteve Reinhardt
The read() function merely initiates a memory read operation; the data doesn't arrive until the access completes and a response packet is received from the memory system. Thus there's no need to provide a data pointer; its existence is historical. Getting this pointer out of this internal o3 interface sets the stage for similar cleanup in the ExecContext interface. Also found that we were pointlessly setting the contents at this pointer on a store forward (the useful memcpy happens just a few lines below the deleted one).
2016-01-17arch: don't call *Timing functions from *Atomic versionsSteve Reinhardt
The readMemAtomic/writeMemAtomic helper functions were calling readMemTiming/writeMemTiming respectively. This is functionally correct, since the *Timing functions are doing the same access initiation operation as the *Atomic functions (just that the *Atomic versions also complete the access in line). It also provides for some (very minimal) code reuse. Unfortunately, it's potentially pretty confusing, since it makes it look like the atomic accesses are somehow being converted to timing accesses. It also gets in the way of specializing the timing interface (as will be done in a future patch).
2016-01-17arch: get rid of unused LargestRead typedefSteve Reinhardt
2016-01-17sim: don't ignore SIG_TRAPSteve Reinhardt
By ignoring SIG_TRAP, using --debug-break <N> when not connected to a debugger becomes a no-op. Apparently this was intended to be a feature, though the rationale is not clear. If we don't ignore SIG_TRAP, then using --debug-break <N> when not connected to a debugger causes the simulation process to terminate at tick N. This is occasionally useful, e.g., if you just want to collect a trace for a specific window of execution then you can combine this with --debug-start to do exactly that. In addition to not ignoring the signal, this patch also updates the --debug-break help message and deletes a handful of unprotected calls to Debug::breakpoint() that relied on the prior behavior.
2016-01-17stats: update SPARC FS statsSteve Reinhardt
The fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic test was broken for so long that, now that it's working again, the stats output is out of date. This changeset updates the outputs, on the assumption that the stats changes are all valid differences due to other changes made while it was broken.
2016-01-15dev, arm: Add a platform with support for both aarch32 and aarch64Andreas Sandberg
Add a platform with support for both aarch32 and aarch64. This platform implements a subset of the devices in a real Versatile Express and extends it with some gem5-specific functionality. It is in many ways similar to the old VExpress_EMM64 platform, but supports the following new features: * Automatic PCI interrupt assignment * PCI interrupts allocated in a contiguous range. * Automatic boot loader selection (32-bit / 64-bit) * Cleaner memory map where gem5-specific devices live in CS5 which isn't used by current Versatile Express platforms. * No fake devices. Devices that were previously faked will be removed from the device tree instead. * Support for 510 GiB contiguous memory
2016-01-15dev, arm: Add support for automatic PCI interrupt routingAndreas Sandberg
Add support for automatic PCI interrupt routing using a device's ID on the PCI bus. Our current DTBs typically tell the kernel that we do this or something similar when declaring the PCI controller. This changeset adds an option to make the simulator behave in the same way. Interrupt routing can be selected by setting the int_policy parameter in the GenericArmPciHost. The following values are supported: * ARM_PCI_INT_STATIC: Use the old static routing policy using the interrupt line from a device's configurtion space. * ARM_PCI_INT_DEV: Use device number on the PCI bus to map to an interrupt in the GIC. The interrupt is computed as: gic_int = int_base + (pci_dev % int_count) * ARM_PCI_INT_PIN: Use device interrupt pin on the PCI bus to map to an interrupt in the GIC. The PCI specification reserves pin ID 0 for devices without interrupts, the interrupt therefore computed as: gic_int = int_base + ((pin - 1) % int_count)
2016-01-11mem: fix bug in packet access endianness changesSteve Reinhardt
The new Packet::setRaw() method incorrectly still contained an htog() conversion. As a result, calls to the old set() method (now defined as setRaw(htog(v))) underwent two htog conversions, which breaks things when htog() is not a no-op. Interestingly the only test that caught this was a SPARC boot test, where an IsaFake device with a non-zero return value was getting swapped twice resulting in a register getting loaded with 0x100000000000000 instead of 1. (Good reason for keeping SPARC around, perhaps?)
2016-01-11scons: Enable -Wextra by defaultAndreas Hansson
Make best use of the compiler, and enable -Wextra as well as -Wall. There are a few issues that had to be resolved, but they are all trivial.
2016-01-11ext: Replace gzstream with iostream3 from zlib to avoid LGPLAndreas Hansson
This patch replaces the gzstream zlib wrapper with the iostream3 wrapper provided as part of zlib contributions. The main reason for the switch is to avoid including LGPL in the default gem5 build. iostream3 is provided under a more permissive license: The code is provided "as is", with the permission to use, copy, modify, distribute and sell it for any purpose without fee.
2016-01-11configs: Fix inheritance of HMCSystem and cleanup spacingAndreas Hansson
Minor fix to ensure the HMCSystem can actually be instantiated (SimObject cannot be created). Also address some spacing issues.
2016-01-07config: Updates for distributed gem5 simulationsGabor Dozsa
2016-01-07dev: Distributed Ethernet link for distributed gem5 simulationsGabor Dozsa
Distributed gem5 (abbreviated dist-gem5) is the result of the convergence effort between multi-gem5 and pd-gem5 (from Univ. of Wisconsin). It relies on the base multi-gem5 infrastructure for packet forwarding, synchronisation and checkpointing but combines those with the elaborated network switch model from pd-gem5. --HG-- rename : src/dev/net/multi_etherlink.cc => src/dev/net/dist_etherlink.cc rename : src/dev/net/multi_etherlink.hh => src/dev/net/dist_etherlink.hh rename : src/dev/net/multi_iface.cc => src/dev/net/dist_iface.cc rename : src/dev/net/multi_iface.hh => src/dev/net/dist_iface.hh rename : src/dev/net/multi_packet.hh => src/dev/net/dist_packet.hh
2016-01-07pseudo inst,util: Add optional key to initparam pseudo instructionGabor Dozsa
The key parameter can be used to read out various config parameters from within the simulated software.
2015-12-31mem: add CacheVerbose debug flag, filter noisy DPRINTFsSteve Reinhardt
Some of the DPRINTFs added to the classic cache in cset 45df88079f04, while useful to those unfamiliar with the cache code, end up being noise when you're familiar with the code but are trying to debug tricky protocol issues. (Particularly getting two messages from each cache as it receives a snoop request then declares that there was no match.) This patch introduces a CacheVerbose debug flag, and moves a subset of the added DPRINTFs into that category, so that Cache by itself returns to being a more succinct summary of cache activity. Also added a CacheAll compound flag to turn on all the cache-related debug flags (other than CacheTags, which you *really* have to want badly to turn it on, IMO).
2015-12-31mem: Do not rely on the NeedsWritable flag for responsesAndreas Hansson
This patch removes the NeedsWritable flag for all responses, as it is really only the request that needs a writable response. The response, on the other hand, should in these cases always provide the line in a writable state, as indicated by the hasSharers flag not being set. When we send requests that has NeedsWritable set, the response will always have the hasSharers flag not set. Additionally, there are cases where the request did not have NeedsWritable set, and we still get a writable response with the hasSharers flag not set. This never happens on snoops, but is used by downstream caches to pass ownership upstream. As part of this patch, the affected response types are updated, and the snoop filter is similarly modified to check only the hasSharers flag (as it should). A sanity check is also added to the packet class, asserting that we never look at the NeedsWritable flag for responses. No regressions are affected.
2015-12-31mem: Do not allocate space for packet data if not neededAndreas Hansson
This patch looks at the request and response command to determine if either actually has any data payload, and if not, we do not allocate any space for packet data. The only tricky case is where the command type is changed as part of the MSHR functionality. In these cases where the original packet had no data, but the new packet does, we need to explicitly call allocate().
2015-12-31mem: Do not alter cache block state on uncacheable snoopsAndreas Hansson
This patch ensures we do not respond with a Modified (dirty and writable) line if the request is uncacheable, and that the cache responding retains the line without modifying the state (even if responding).
2015-12-31mem: Make cache terminology easier to understandAndreas Hansson
This patch changes the name of a bunch of packet flags and MSHR member functions and variables to make the coherency protocol easier to understand. In addition the patch adds and updates lots of descriptions, explicitly spelling out assumptions. The following name changes are made: * the packet memInhibit flag is renamed to cacheResponding * the packet sharedAsserted flag is renamed to hasSharers * the packet NeedsExclusive attribute is renamed to NeedsWritable * the packet isSupplyExclusive is renamed responderHadWritable * the MSHR pendingDirty is renamed to pendingModified The cache states, Modified, Owned, Exclusive, Shared are also called out in the cache and MSHR code to make it easier to understand.
2015-07-20ruby: slicc: have a static MachineTypeTony Gutierrez
This patch is imported from reviewboard patch 2551 by Nilay. This patch moves from a dynamically defined MachineType to a statically defined one. The need for this patch was felt since a dynamically defined type prevents us from having types for which no machine definition may exist. The following changes have been made: i. each machine definition now uses a type from the MachineType enumeration instead of any random identifier. This required changing the grammar and the *.sm files. ii. MachineType enumeration defined statically in RubySlicc_Exports.sm. * * * normal protocol fixes for nilay's parser machine type fix
2015-07-20ruby: slicc: remove support for single machine, multiple typesTony Gutierrez
This patch is imported from reviewboard patch 2550 by Nilay. It was possible to specify multiple machine types with a single state machine. This seems unnecessary and is being removed.
2015-12-30stats: more updates due to PCI changesSteve Reinhardt
A couple of the long regressions have been showing as CHANGED since 11244:a2af58a06c4e despite the updates in 11245:1c5102c0a7a9. The x86 regression looks like it was just missed, but it's not clear why the ARM one is giving different results (perhaps a non-determinism between zizzer and wherever the updated results were run?).
2015-12-28tests: update EIO reference outputsSteve Reinhardt
2015-12-28mem: Explicitly check MSHR snoops for cases not dealt withAndreas Hansson
Add a sanity check to make it explicit that we currently do not allow an I/O coherent agent to directly issue writes into the coherent part of the memory system (it has to go via a cache, and get transformed into a read ex, upgrade or invalidation).
2015-12-28mem: Remove unused cache squash functionalityAndreas Hansson
This patch removes the unused squash function from the MSHR queue, and the associated (and also unused) threadNum member from the MSHR.
2015-12-28mem: Avoid unecessary checks when creating HardPFReq in cacheAndreas Hansson
The checks made before sending out a HardPFReq were unecessarily complex, and checked for cases that never occur. This patch tidies it up.
2015-12-28mem: Do not use sender state to track forwarded snoops in cacheAndreas Hansson
This patch changes how the cache tracks which snoops are forwarded, and which ones are created locally. Previously the identification was based on an empty sender state of a specific class, but this method fails to distinguish which cache actually attached the sender state. Instead we use the same mechanism as the crossbar, and keep track of the requests that have outstanding snoops.