Age | Commit message (Collapse) | Author |
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Move check for loops outside, since half the call sites
end up working around it anyway. Return integer port ID
instead of port object pointer.
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extra : convert_revision : 4c31fe9930f4d1aa4919e764efb7c50d43792ea3
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Also make default 0, and make that mean run forever.
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Also added comments to document treespec format.
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See Flyspray #281.
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Note that we should *not* print pointer values in DPRINTFs as
these needlessly clutter tracediff output.
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extra : convert_revision : b8894d26e1ca7a6c9b736500accdaa53bfb09558
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src/cpu/simple/timing.cc:
Fix another SC problem.
src/mem/cache/cache_impl.hh:
Forgot to call makeTimingResponse() on uncached timing responses.
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extra : convert_revision : 5a5a58ca2053e4e8de2133205bfd37de15eb4209
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src/cpu/simple/timing.cc:
Fix swap/stq_c command bug.
src/mem/packet.cc:
Fix incorrect LoadLockedReq command response field.
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extra : convert_revision : 7a4523be900bc2c9b1bdf2d372ce55f89ae58ae5
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Fix atomic timing issue.
src/mem/bus.cc:
Fix atomic timing issue.
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Handled by Packet::checkFunctional() now.
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extra : convert_revision : 63642254e2789c80a369ac269f317ec054ffe3c0
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(they function as adjectives not nouns)
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Stats pretty much line up with old code, except:
- bug in old code included L1 latency in L2 miss time, making it too high
- UniCoherence did cache-to-cache transfers even from non-owner caches,
so occasionally the icache would get a block from the dcache not the L2
- L2 can now receive ReadExReq from L1 since L1s have coherence
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extra : convert_revision : 5052c1a1767b5a662f30a88f16012165a73b791c
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now encoded in cmd field.
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into vm1.(none):/home/stever/bk/newmem-cache2
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src/arch/mips/isa/decoder.isa:
commment out deret instruction for now...
src/arch/mips/isa/formats/fp.isa:
edit fp format
src/arch/mips/isa/formats/mem.isa:
fix for basic store instructions
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into vm1.(none):/home/stever/bk/newmem-cache2
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Change target overflow from assertion to warning.
src/mem/cache/cache_impl.hh:
Change target overflow from assertion to warning.
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src/mem/cache/tags/lru.cc:
Add some replacement DPRINTFs
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src/mem/cache/cache_impl.hh:
Handle grants with no packet.
src/mem/cache/miss/mshr.cc:
Fix MSHR snoop hit handling.
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extra : convert_revision : f365283afddaa07cb9e050b2981ad6a898c14451
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sure we don't re-request bus prematurely. Use callback to
avoid calling sendRetry() recursively within recvTiming.
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into vm1.(none):/home/stever/bk/newmem-cache2
src/base/traceflags.py:
Hand merge.
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extra : convert_revision : 9e7539eeab4220ed7a7237457a8f336f79216924
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src/cpu/memtest/memtest.cc:
Need to set packet source field so that response from cache
doesn't run into assertion failure when copying source to dest.
src/mem/packet.hh:
Copy source field when copying packets.
Assert that source is valid before copying it to dest
when turning packets around.
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extra : convert_revision : 09e3cfda424aa89fe170e21e955b295746832bf8
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ControlBitfieldOPerand to ISA Parser. Now, while things do build, we have to fix broken functionality...
src/arch/isa_parser.py:
add back deleted writeback in Control Operand
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into vm1.(none):/home/stever/bk/newmem-cache2
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extra : convert_revision : aa50af3094f5d459f75b514179b6e3ec5e0bf1df
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src/arch/mips/SConscript:
"mips import pt.1".
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extra : convert_revision : 2e393341938bebf32fb638a209262d074fad4cc1
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into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/newmem-o3-micro
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extra : convert_revision : 3fa3fa4544ff8c9d2135e1befe6c8f4757006a2a
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mcf has a reduced input size, and most of the other changes are for a change in how branch mispredicts work which makes things more accurate.
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