gem5 - gem5

Age	Commit message (Expand)	Author
2011-04-15	debug: create a Debug namespace	Nathan Binkert
2011-04-15	includes: fix up code after sorting	Nathan Binkert
2011-04-15	includes: sort all includes	Nathan Binkert
2011-04-15	style: add sort_includes to the style hook	Nathan Binkert
2011-04-15	style: move style verifiers into classes	Nathan Binkert
2011-04-15	style: add a user interface wrapper class	Nathan Binkert
2011-04-15	util: python implementation of a routine that will sort includes	Nathan Binkert
2011-04-15	region: add a utility class for keeping track of regions of some range	Nathan Binkert
2011-04-15	SortedDict: add functions for getting ranges of keys, values, items	Nathan Binkert
2011-04-15	python: figure out if the m5.internal package exists even with demandimport	Nathan Binkert
2011-04-13	refcnt: Update doxygen comments	Nathan Binkert
2011-04-13	refcnt: Inline comparison functions	Nathan Binkert
2011-04-13	main: separate out interact() so it can be used by other functions	Nathan Binkert
2011-04-13	util: fix the language type function	Nathan Binkert
2011-04-12	ARM: Fix stats for ARM_SE checkpoint restore fix.	Ali Saidi
2011-04-10	ARM: Fix checkpoint restoration in ARM_SE.	Ali Saidi
2011-04-10	ARM: Get rid of some comments/todos that no longer apply.	Ali Saidi
2011-04-06	ruby: fixes to support more types of RubyRequests	Brad Beckmann
2011-04-04	ARM: Update stats for default inclusion of CF adapter.	Ali Saidi
2011-04-04	ARM: Include IDE/CF controller by default in PBX model.	Ali Saidi
2011-04-04	Sim: Fix Simulation.py to allow more than 1 core for standard switching.	Anthony Gutierrez
2011-04-04	ARM: Update stats for previous changes.	Ali Saidi
2011-04-04	ARM: Use CPU local lock before sending load to mem system.	Ali Saidi
2011-04-04	ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.	Ali Saidi
2011-04-04	ARM: Fix bug in MicroLdrNeon templates for initiateAcc().	Ali Saidi
2011-04-04	ARM: Cleanup and small fixes to some NEON ops to match the spec.	William Wang
2011-04-04	ARM: Cleanup implementation of ITSTATE and put important code in PCState.	Ali Saidi
2011-04-04	ARM: Fix m5op parameters bug.	Ali Saidi
2011-04-04	ARM: Tag appropriate instructions as IsReturn	Ali Saidi
2011-04-04	ARM: Fix table walk going on while ASID changes error	Ali Saidi
2011-04-04	CPU: Remove references to memory copy operations	Ali Saidi
2011-04-04	O3: Update stats for memory order violation checking patch.	Ali Saidi
2011-04-04	O3: Tighten memory order violation checking to 16 bytes.	Ali Saidi
2011-04-04	IDE: Support x86, Alpha, and ARM use of the IDE controller.	Ali Saidi
2011-04-04	ARM: Fix checkpointing case where PL111 is powered off.	Ali Saidi
2011-04-04	ARM: Remove debugging warn that was accidently left in.	Ali Saidi
2011-04-04	ARM: Fix multiplication error in udelay	Ali Saidi
2011-04-01	hammer: fixed dma uniproc error	Brad Beckmann
2011-03-31	CacheMemory: add allocateVoid() that is == allocate() but no return value.	Lisa Hsu
2011-03-31	Ruby: Simplify SLICC and Entry/TBE handling.	Lisa Hsu
2011-03-31	Ruby: Add new object called WireBuffer to mimic a Wire.	Lisa Hsu
2011-03-31	Ruby: have the rubytester pass contextId to Ruby.	Lisa Hsu
2011-03-31	Ruby: enable multiple sequencers in one controller.	Lisa Hsu
2011-03-31	Ruby: pass Packet->Req->contextId() to Ruby.	Lisa Hsu
2011-03-31	Ruby: Bug in SLICC forgot semicolon at end of code.	Lisa Hsu
2011-03-29	sim: typecast Tick to UTick for eventQ assert	Korey Sewell
2011-03-29	Power: Fix compilation.	Gabe Black
2011-03-28	This patch supports cache flushing in MOESI_hammer	Somayeh Sardashti
2011-03-28	Config: Import math in MI_example.py	Nilay Vaish
2011-03-26	tests: update reference outputs for ruby cache index change	Steve Reinhardt