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AgeCommit message (Expand)Author
2015-02-26Ruby: Update backing store option to propagate through to all RubyPortsJason Power
2015-02-16config: Add memcheck stress testAndreas Hansson
2015-02-16cpu: TrafficGen sinks snoops without complainingAndreas Hansson
2015-02-16mem: Fix initial value problem with MemCheckerStephan Diestelhorst
2015-02-16dev: Fix undefined behaviuor in i8254xGBeAndreas Hansson
2015-02-16arm: Wire up the GIC with the platform in the base classAndreas Sandberg
2015-02-16mem: mmap the backing store with MAP_NORESERVEAndreas Hansson
2015-02-16mem: Use the range cache for lookup as well as accessAndreas Hansson
2015-02-16arch: Make readMiscRegNoEffect const throughoutAndreas Hansson
2015-01-16config: add --root-device machine parameterCurtis Dunham
2015-02-16arm: Merge ISA files with pseudo instructionsAndreas Sandberg
2015-02-16cpu: add support for outputing a protobuf formatted CPU traceAli Saidi
2015-02-11mem: Clarification of packet crossbar timingsMarco Balboni
2015-02-11mem: Clarify usage of latency in the cacheMarco Balboni
2015-02-11style: Fix broken m5format commandAndreas Sandberg
2015-02-11style: Fix incorrect style checker option nameAndreas Sandberg
2015-02-11config: Revamp memtest to allow testers on any levelAndreas Hansson
2015-02-11stats: Bump the MemTest regression statsAndreas Hansson
2015-02-11cpu: Tidy up the MemTest and make false sharing more obviousAndreas Hansson
2015-02-11sim: Move the BaseTLB to src/arch/generic/Andreas Sandberg
2015-02-11base: Add compiler macros to add deprecation warningsAndreas Sandberg
2015-02-11base: Do not dereference NULL in CompoundFlag creationAndreas Hansson
2015-02-11dev: Remove unused system pointer in the Platform base classAndreas Sandberg
2015-02-06cpu: Idle CPU status logic revisedAlexandru Dutu
2015-02-05config: rename 'file' varSteve Reinhardt
2015-02-05config: make M5_PATH a real search pathSteve Reinhardt
2015-02-03mem: Clarify express snoop behaviourAndreas Hansson
2015-02-03mem: Clarify cache behaviour for pending dirty responsesAndreas Hansson
2015-02-03base: add an accessor and operators ==,!= to address rangesCurtis Dunham
2015-02-03config: Add XOR hashing to the DRAM channel interleavingAndreas Hansson
2015-02-03base: Add XOR-based hashed address interleavingAndreas Hansson
2015-02-03config: Adjust DRAM channel interleaving defaultsAndreas Hansson
2015-02-03style: Update the style checker to handle new include orderAndreas Sandberg
2015-02-03sim: Remove test for non-NULL this in EventAndreas Sandberg
2015-02-03dev: Correctly clear interrupts in VirtIO PCIAndreas Sandberg
2015-02-03scons: Avoid implicit command dependenciesAndreas Hansson
2014-12-19sim: prioritize async events; prevent starvationCurtis Dunham
2015-02-03cpu: Ensure timing CPU sinks response before sending new requestAndreas Hansson
2015-02-03config: Fix typo in Float paramGeoffrey Blake
2015-01-30config: arm: fix os_flagsMalek Musleh
2015-01-25arm: always set the IsFirstMicroop flagAli Saidi
2015-01-25sim: Clean up InstRecordAli Saidi
2015-01-25cpu: Remove all notion that we know when the cpu is misspeculating.Ali Saidi
2015-01-25cpu: Put all CPU instruction tracers in a single fileAli Saidi
2015-01-25cpu: remove legion tracerAli Saidi
2014-12-23sim: fix reference counting of PythonEventCurtis Dunham
2015-01-22mem: Remove unused Packet src and dest fieldsAndreas Hansson
2015-01-22mem: Remove Packet source from ForwardResponseRecordAndreas Hansson
2015-01-22mem: Remove unused RequestState in the bridgeAndreas Hansson
2015-01-22mem: Always use SenderState for response routing in RubyPortAndreas Hansson
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