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AgeCommit message (Expand)Author
2012-12-11ruby: change slicc to allow for constructor argsNilay Vaish
2012-12-11ruby: add a prefetcherNilay Vaish
2012-12-11ruby: add functions for computing next stride/page addressNilay Vaish
2012-12-06regression test: update a couple of config.ini filesNilay Vaish
2012-12-06TournamentBP: Fix some bugs with table sizes and countersErik Tomusk
2012-12-06inorder cpu: add missing DPRINTF argumentMalek Musleh
2012-12-06o3 cpu: remove some unused buggy functions in the lsqNathanael Premillieu
2012-11-19config: Fix description of checkpoint option from cycle to tickAndreas Hansson
2012-11-16sim: have a curTick per eventqNilay Vaish
2012-11-10regressions: stats update due to ruby functional access patchNilay Vaish
2012-11-10ruby: support functional accesses in garnet flexible networkNilay Vaish
2012-11-10ruby: bug in functionalRead, revert recent changesNilay Vaish
2012-11-08mem: Fix DRAM draining to ensure write queue is emptyAndreas Hansson
2012-11-03x86, util: add m5_writefile to m5op_x86.SLluis Vilanova
2012-11-02ruby: reset and dump stats along with reset of the systemHamid Reza Khaleghzadeh ext:(%2C%20Lluc%20Alvarez%20%3Clluc.alvarez%40bsc.es%3E%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2012-11-02mem: fix use after free issue in memories until 4-phase work complete.Ali Saidi
2012-11-02update stats for preceeding changesAli Saidi
2012-11-02mem: Add support for writing back and flushing cachesAndreas Sandberg
2012-11-02sim: Add drain methods to request additional cleanup operationsAndreas Sandberg
2012-11-02sim: Add SWIG interface for SerializableAndreas Sandberg
2012-11-02python: Rename doDrain()->drain() and make it do the right thingAndreas Sandberg
2012-11-02sim: Reuse the code to change memory mode.Andreas Sandberg
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-11-02cpu: O3 add a header declaring the DerivO3CPUAndreas Sandberg
2012-11-02cpu: Add header files for checker CPUsAndreas Sandberg
2012-11-02dev: Fix ethernet device inheritance structureAndreas Sandberg
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-11-02pci: Make Python wrapper cast to the right typeAndreas Sandberg
2012-11-02mips: Remove unused Python fileAndreas Sandberg
2012-11-02dev: Add missing inline declarationsAndreas Sandberg
2012-11-02base: Add missing header file to addr_range.hh.Andreas Sandberg
2012-10-09m5: Expose m5 pseudo-instructions to C/C++ via a static libraryJames Clarkson
2012-11-02ARM: dump stats and process info on context switchesDam Sunwoo
2012-11-02base: Fix a few incorrectly handled print format casesChander Sudanthi
2012-11-02base: split out the VncServer into a VncInput and Server classesChander Sudanthi
2012-11-02ISA: generic Linux thread info supportDam Sunwoo
2012-11-02sim: Fix as issue where exit events on instr queues are used after freed.Ali Saidi
2012-11-02o3: Fix a couple of issues with the local predictor.Mrinmoy Ghosh
2012-11-02Partly revert [4f54b0f229b5] and move draining to m5.changeToTimingAndreas Sandberg
2012-10-31mem: Fix typo in port commentsAndreas Hansson
2012-10-31stats: Update stats for fixed simple-atomic-mp configAndreas Hansson
2012-10-31config: Fix a typo in the simple-atomic-mp configurationAndreas Hansson
2012-10-30stats: Update stats for unified cache configurationAndreas Hansson
2012-10-30config: Unify caches used in regressions and adjust L2 MSHRsAndreas Hansson
2012-10-27regressions: update stats for ruby fs testNilay Vaish
2012-10-27ruby: set the is_icache param for cachesMalek Musleh
2012-10-27Ruby: Use block size in configuring directory bits in addressJason Power ext:(%2C%20Joel%20Hestness%20%3Chestness%40cs.wisc.edu%3E)
2012-10-26config: Add a check for fastmem only used with Atomic CPUAndreas Hansson
2012-10-26config: Remove unused mem_size in fs.pyAndreas Hansson
2012-10-26config: Fix the cache class naming in regression scriptsAndreas Hansson